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| umarcor | Hi! I was wondering what is the format used in Yosys -> Quartus workflows. | 02:32 |
|---|---|---|
| umarcor | I saw Quartus -> VQM -> vqm2blif -> BLIF -> VPR. | 02:33 |
| umarcor | Is Yosys -> ??? -> Quartus supported? | 02:34 |
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| Lofty | umarcor: hi, I'm the developer of the Yosys frontend for Intel chips | 09:30 |
| Lofty | Yosys can output directly to VQM for Quartus | 09:30 |
| Lofty | This is in fact mainly how I use it | 09:31 |
| umarcor | Lofty: hi! so, is VQM used either as an input from open source tools to Quartus os as an output from Quartus to open source tools? | 09:32 |
| Lofty | The former | 09:32 |
| umarcor | No JSON, EDIF, BLIF or other formats are used/supported by Quartus? | 09:32 |
| Lofty | Fundamentally though it's a Verilog netlist of cells | 09:32 |
| Lofty | EDIF is apparently supported, but EDIF is a horrendous format | 09:32 |
| umarcor | Note that I'm asking this because I'm drawing a diagram of the ecosystem. | 09:33 |
| Lofty | Output to nextpnr would use JSON | 09:33 |
| umarcor | I don't have any strong interest on one format or the other, but just understanding what the current state is. | 09:33 |
| Lofty | And I presently have no intentions of using VPR. | 09:33 |
| umarcor | How do you get from VQM to a bitstream for Intel devices? | 09:34 |
| Lofty | Well, Yosys takes in the Verilog and produces a .vqm file | 09:34 |
| umarcor | Is it Yosys -> VQM -> Quartus -> Bitstream? | 09:34 |
| Lofty | Yes | 09:35 |
| umarcor | Thanks! | 09:35 |
| umarcor | Out of curiosity, did you try VHDL or are you a Verilog only user? | 09:35 |
| Lofty | VHDL input for Yosys would use the GHDL plugin | 09:36 |
| Lofty | Which seems to work okay | 09:36 |
| umarcor | Indeedd... I'm an active contributor to GHDL. | 09:36 |
| umarcor | I take care of the docs, CI, etc. | 09:36 |
| umarcor | That's how I approached Yosys and Symbiflow. | 09:37 |
| Lofty | I wouldn't really call the Intel flow part of Symbiflow any more than I would call the ECP5 flow part of Symbiflow | 09:37 |
| Lofty | But that's neither here nor there | 09:37 |
| Lofty | 'the Intel flow' is codenamed Project Mistral, FWIW | 09:39 |
| umarcor | However, Quartus -> VQM -> BLIF -> VPR is a documented flow. Does that fit into Symbiflow? | 09:40 |
| umarcor | Is this the official repo of Project Mistral? https://github.com/Ravenslofty/mistral | 09:42 |
| Lofty | umarcor: that flow seems like the worst of both worlds | 09:48 |
| Lofty | Especially when you consider that Quartus uses a heavily modified VPR internally anyway | 09:49 |
| Lofty | [09:42:54] umarcor: Is this the official repo of Project Mistral? https://github.com/Ravenslofty/mistral <--- 'kinda' | 09:49 |
| umarcor | In fact, I feel that Yosys -> BLIF -> VPR makes more sense than using Quartus. Nonetheless, I'm trying to document what's possible, to then discuss what's sensible. | 09:51 |
| Lofty | Well, since Yosys doesn't output Intel netlists to BLIF that's distinctly *not* possible | 09:53 |
| umarcor | Is it not possible or not implemented? | 09:53 |
| Lofty | "I won't support it" | 09:53 |
| umarcor | Oh, that's ok. I'm not implying any of the commented workflows needs to be actively supported. | 09:54 |
| Lofty | The chips I'm focusing on are the Cyclone V and Cyclone 10 GX. | 09:54 |
| Lofty | VPR does not have models of those, to my knowledge | 09:54 |
| Lofty | So while adding BLIF output is a one-liner, I'm not writing the VPR models for the hardware | 09:56 |
| umarcor | VPR is transitioning very fast from dealing with theoretical models to supporting Xilinx devices. Hence, it is possible that Intel devices are supported in VPR in the not far future. | 09:57 |
| umarcor | Anyway, thanks a lot for the insight about what's possible at now, and what are your expectations. | 09:57 |
| umarcor | much appreciated | 09:58 |
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| sf-slack | <pgielda> Well, VPR already supports Xilinx and Quicklogic devices, so the transition happened. But its important for the health of Open Source ecosystem that multiple tools are supported and are interoperable. | 10:20 |
| sf-slack | <pgielda> (unlike "vendor" tools that are usually not) | 10:20 |
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| umarcor | pgielda: is VPR the only supported toolchain for Quicklogic devices? | 10:38 |
| sf-slack | <kgugala> @umacor: VPR is the only opensource toolchain for QL devices | 10:41 |
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| umarcor | kgugala: do you mean that https://www.quicklogic.com/software/legacy-fpga-tools/ exists? | 10:48 |
| tpb | Title: QuickLogic Legcy FPGA Tools | QuickLogic Corporation (at www.quicklogic.com) | 10:48 |
| umarcor | or is there a non-legacy non-opensource alternative? | 10:48 |
| sf-slack | <kgugala> QL switched fully to open source | 10:49 |
| sf-slack | <kgugala> the legacy proprietary tool sare available on the website you linked | 10:50 |
| umarcor | thanks! | 10:57 |
| -_whitenotifier-f- [symbiflow-tools-package-manager] kgugala opened issue #3: Add format checker to CI - https://git.io/JTX7Q | 11:11 | |
| -_whitenotifier-f- [symbiflow-tools-package-manager] kgugala opened issue #4: Add License checker to CI - https://git.io/JTX75 | 11:11 | |
| -_whitenotifier-f- [symbiflow-tools-package-manager] kgugala opened issue #5: Update README - https://git.io/JTX5C | 11:18 | |
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