Wednesday, 2020-10-14

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sf-slack<olof.kindgren> Where can I find the code for the Quickfeather factory FPGA image?10:38
sf-slack<kgugala> is it USB2Serial? https://github.com/QuickLogic-Corp/s3-gateware10:44
tpbTitle: GitHub - QuickLogic-Corp/s3-gateware: Gateware (HDL IPs) for EOS S3 MCU+eFPGA SoC (at github.com)10:44
sf-slack<olof.kindgren> Probably yes. Noticed there's a bit of my old code inside it as well :)11:08
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-_whitenotifier-f- [python-sdf-timing] christian-lanius opened issue #42: Conditions are not matching HDL literals - https://git.io/JTYq611:59
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mithrokgugala: https://git.m-labs.hk/m-labs/zynq-rs15:57
tpbTitle: M-Labs/zynq-rs: Bare-metal Rust on Zynq-7000 - zynq-rs - M-Labs Git (at git.m-labs.hk)15:57
sf-slack<kgugala> this is pretty cool15:58
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sf-slack<mgielda> need to run it in renode now17:10
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sf-slack<olof.kindgren> Alright then. The quicklogic symbiflow backend is merged into edalize now20:44
sf-slack<kgugala> Awesome20:44
sf-slack<olof.kindgren> Haven't had time to look closer at an SWD cable though20:46
sf-slack<olof.kindgren> Also not sure about the pin numbering in the pcf file. Looking at the schematics of the quickfeather board, each pin has a plain number (which I guess is the physical package pin number) and a IO_ number. Which is the one I should enter into the pcf?20:52
sf-slack<olof.kindgren> e.g. is the red LED 22 or 3420:53
sf-slack<olof.kindgren> ?20:53
sf-slack<olof.kindgren> ok, using 22 results in an error stating that this pin is dedicated for a PB-SDIOMUX. Is there any documentation around the pinning somewhere?20:55
sf-slack<olof.kindgren> If anyone's up for some testing I have an FPGA image here that is supposed to implement three SERV cores and continously output status on the red LED21:12
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-_whitenotifier-f- [symbiflow-examples] mithro opened issue #61: Add quadcore VexRISCV example from Antmicro blog post - https://git.io/JTOGX21:59
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