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| ske33 | Thanks sf-slack .......... :) | 02:56 |
|---|---|---|
| sorear | sf-slack is a bridge bot, the last user who spoke through it was timo.callahan | 03:04 |
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| sf-slack | <timo.callahan> It's confusing :) | 03:09 |
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| -_whitenotifier-3- [symbiflow-arch-defs] rw1nkler opened issue #1645: Incorrect PLL-BUFG-BUFGMUX handling - https://git.io/JJjWk | 10:22 | |
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| jopdorp | sup y'allll | 19:17 |
| jopdorp | :p | 19:17 |
| jopdorp | I'm Jegor | 19:17 |
| jopdorp | I'm a software engineer and a starting fpga enthousiast | 19:18 |
| jopdorp | I've implemented a couple of projects in verilog using verilator, icarus and modelsim(the compiler from quartus) | 19:18 |
| jopdorp | I really like using verilator and icarus because open source rocks! | 19:19 |
| jopdorp | now the thing is that my fpga is a Cyclone V | 19:19 |
| jopdorp | I have that because of the MisTer project | 19:19 |
| jopdorp | Is anyone looking at Cyclone V support, and if not, how would I start on Cyclone V myself? | 19:20 |
| jopdorp | i found the yosys and vtr-verilog-to-routing repos | 19:23 |
| jopdorp | is there a core symbiflow repo? | 19:24 |
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| Lofty | jopdorp: Hi, I'm working on reversing the Cyclone V along with Sarayan (who isn't in this channel) | 19:46 |
| Lofty | Well, to be more precise, we've mostly reversed Quartus to obtain information on the Cyclone V | 19:46 |
| Lofty | Work for it isn't really associated with Symbiflow, so we work in #prjmistral instead | 19:47 |
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| jopdorp | Lofty: that's awesome I'm keen to have a look | 20:29 |
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