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| sf-slack | <timo.callahan> Hi @mholenko, I'm still working on LiteX differences between timvideos and the tensorflow demo. It seems the base CSR address has changed -- I see 0x8200000 and 0xE0000000, respectively. The overlay created by generate-zephyr-dts.py doesn't have any information about these....is the CSR base address determined somehow else? Thanks! | 08:03 |
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| sf-slack | <kgugala> @timo.callahan litex_term requires software running on the programmed CPU that will receive the UART transferred data and write it to RAM. If you want to use it with your Zephyr app, you need to include this functionality in the app (probably you can "borrow" some code from LiteX' Bios) | 08:09 |
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| sf-slack | <mholenko> @timo.callahan: what addresses do you see in the generated overlay DT (it's located in buildenv's build/platform/software/zephyr directory)? The `reg` property should already contain a value that is based on the CSR base address (i.e., it should be 0x8200000/0xE0000000 plus some offset) | 08:30 |
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| Lofty | Ping kgugala__ | 14:05 |
| sf-slack | <kgugala> ping about what? | 14:06 |
| Lofty | QuickLogic | 14:06 |
| Lofty | Or specifically synth_quicklogic | 14:06 |
| sf-slack | <kgugala> but what was the question? | 14:07 |
| Lofty | The flop mapping can be simplified a lot by using the `dfflegalize` pass that was recently introduced | 14:07 |
| Lofty | Additionally, you should not map latches unless the fabric is glitchless, because Yosys assumes if latches are mapped they are glitchless | 14:08 |
| sf-slack | <kgugala> I'm working on this right now, just rebased the PR | 14:08 |
| Lofty | Yeah, I saw, just wanted to make sure you were aware | 14:09 |
| sf-slack | <kgugala> need to introduce the dff/latch changes and test it | 14:09 |
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| Lofty | What do the QuickLogic flops initialise to? It's not mentioned in the EOS S3 TRM, as far as I can tell | 14:10 |
| sf-slack | <kgugala> to 0 AFAIK, but have to check this | 14:12 |
| Lofty | Then all you need really is to add `dfflegalize -cell $_DFFSRE_PPPP_ 0` to your flow and map one cell | 14:13 |
| sf-slack | <kgugala> thanks for the hints, I'll update the code and push the changes | 14:20 |
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| tnt | kgugala: Is the direct LUT -> FF path implemented now ? Also true LUT4 mapping (rather than mapping to 2 LUT3 + FMUX) ? | 14:39 |
| sf-slack | <kgugala> @tnt: LUT4 works, LUT -> FF support is here https://github.com/antmicro/symbiflow-arch-defs/tree/lut-ff-direct, will open a PR once this https://github.com/QuickLogic-Corp/python-symbiflow-v2x/pull/3 is merged | 14:42 |
| tpb | Title: Allow specification of multiple pack patterns by mkurc-ant · Pull Request #3 · QuickLogic-Corp/python-symbiflow-v2x · GitHub (at github.com) | 14:42 |
| tnt | kgugala: Ah nice tx for the pointers. | 14:43 |
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| -_whitenotifier-b- [sv-tests] hzeller opened issue #972: Sorting tool columns: doesn't take partial passing into account - https://git.io/JJamV | 15:00 | |
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| -_whitenotifier-b- [fpga-tool-perf] mithro opened issue #198: Define a set of tests which run on all devices - https://git.io/JJas6 | 16:00 | |
| -_whitenotifier-b- [FPGA-Tool-Performance-Visualization-Library] TypingKoala opened issue #15: Legacy Icestorm Processor - https://git.io/JJasi | 16:01 | |
| -_whitenotifier-b- [fpga-tool-perf] mithro opened issue #199: Make sure a test which works for a35t works for all a35t compatible toolchains - https://git.io/JJasx | 16:02 | |
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| andrewb1999 | Does anyone know if it's possible to constrain a top level io to multiple io pads in VPR? | 16:12 |
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| sf-slack | <acomodi> I think this is impossible. As far as I know the io blocks are assigned uniquely to one grid location | 16:19 |
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| sf-slack | <benglines1> I've been having trouble getting bitread to work with Project U-Ray. Here's what I'm doing to run it: `../prjuray/third_party/prjuray-tools/build/tools/bitread --part_file ../prjuray/database/zynqusp/xczu3eg-sfvc784-1-e/part.yaml -o bitstream.bits -z -y ../prjuray/inverter_example_zu3eg/inverter_example.bit` And this is what I'm getting for the output: `Bitstream size: 5865840 bytes` `Config size: 1466409 words` | 16:54 |
| sf-slack | `Part file not found or invalid` To me it looks like the tool built correctly, and the path to the part seems to be correct to me. Does the path that I use to the part file seem correct? Does bitread expect the part.yaml file or something else? | 16:54 |
| sf-slack | <tmichalak> @benglines1 Yes, it requires part.yaml. What is missing in the command you pasted is --architecture UltraScalePlus | 17:08 |
| sf-slack | <tmichalak> This is because the tool supports Spartan6, Series7, US and US+ and Series7 is default for backward compatibility with prjxray | 17:10 |
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| sf-slack | <benglines1> @tmichalak That seemed to work. Thanks! | 17:15 |
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| sf-slack | <timo.callahan> Thanks @kgugala, so basically the serial boot mechanism, but for data. The code on Arty would print the serialboot keyword to uart, then lxterm responds. | 18:13 |
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| -_whitenotifier-b- [FPGA-Tool-Performance-Visualization-Library] TypingKoala opened issue #16: HydraFetcher unable to fetch meta.json of older builds - https://git.io/JJa2e | 21:19 | |
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