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| -_whitenotifier-9- [python-symbiflow-v2x] mkurc-ant opened issue #64: Make V2X use Surelog instead of Yosys - https://git.io/JfsSF | 07:42 | |
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| sf-slack | <p.vanleeuwen> Heya! I'm having troubles installing Project Trellis (multiple attempts on different VMs). As far as I know, I'm following the instructions to the letter. Any tips? | 14:34 |
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| daveshah | What is going wrong? | 14:35 |
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| sf-slack | <timo.callahan> @acomodi -- thanks! | 16:25 |
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| -_whitenotifier-9- [ideas] acomodi opened issue #52: Open FPGA for absolute beginners - https://git.io/JfG34 | 18:18 | |
| -_whitenotifier-9- [ideas] kgugala opened issue #53: Add Contributing Guide to SymbiFlow projects - https://git.io/JfG3g | 18:20 | |
| -_whitenotifier-9- [ideas] acomodi opened issue #54: Cross linking between projects - https://git.io/JfG36 | 18:23 | |
| sf-slack | <timo.callahan> @acomodi: confirmed that with the added XDC file, the litex example's memtest is now OK. | 18:26 |
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| -_whitenotifier-9- [ideas] kgugala opened issue #55: Create a Series of user stories documents - https://git.io/JfG3Q | 18:28 | |
| sf-slack | <acomodi> @timo.callahan Perfect | 18:29 |
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| -_whitenotifier-9- [ideas] kgugala opened issue #56: SymbiFlow projects documentation audit - https://git.io/JfGse | 18:33 | |
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| jfierro | Lot's of crossover with #yosys, but just in case here's a diagram of the Xilinx 7-Series SLICEL architecture that I made: https://raw.githubusercontent.com/jfierro/fpga-doc/master/xilinx/7-Series_SLICEL.svg | 19:19 |
| jfierro | Hope it can be helpful to anyone ^_^ | 19:20 |
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| mithro | Oooh that is a nice diagram | 19:51 |
| gsmecher | very nice! I see Inkscape tags -- but is that Inkscape from scratch? | 20:55 |
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| jfierro | :mithro thanks! | 22:27 |
| jfierro | gsmecher: yes, I did it on Inkscape from zero. Well, it's based on the layout that Vivado gives for an Artix-7 part and the CLB User Guide. Which reminds me, I really should look into getting better at Inkscape, this took longer than I'm comfortable admitting. | 22:29 |
| mithro | jfierro: We are eventually hoping to be able to generate this style of diagram from the verilog | 22:32 |
| jfierro | mithro: that'd be awesome! Drawing pretty vectorized schematics and graph layout is a problem that has always interested me. I might make it my next hobby and see if I can contribute to symbiflow that way. | 22:35 |
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| mithro | jfierro: Have you seen netlistsvg? | 22:37 |
| mithro | jfierro: and http://sphinxcontrib-verilog-diagrams.rtfd.io/ | 22:37 |
| tpb | Title: Sphinx Verilog Diagrams Sphinx Verilog 0.0-19-gdca0472 documentation (at sphinxcontrib-verilog-diagrams.rtfd.io) | 22:37 |
| jfierro | mithro: I hadn't but that looks super interesting, thanks for sharing. | 22:42 |
| ZirconiumX | Hurray for not having diagrams because my priorities are awful | 22:44 |
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| mithro | jfierro: It needs a lot more work, but daniellimws has been helping quite a bit with general documentation stuff | 23:08 |
| mithro | jfierro: https://github.com/nturley/netlistsvg | 23:09 |
| tpb | Title: GitHub - nturley/netlistsvg: draws an SVG schematic from a JSON netlist (at github.com) | 23:09 |
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| mithro | jfierro: Also https://github.com/SymbiFlow/ideas/issues/41 | 23:47 |
| tpb | Title: RTL Schematic View · Issue #41 · SymbiFlow/ideas · GitHub (at github.com) | 23:47 |
| mithro | jfierro: I believe @drom might be hosting a Google Summer of Code student working on that | 23:48 |
| jfierro | I love that symbiflow already has some enhancement ideas as well documented as this :) | 23:55 |
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