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| -_whitenotifier-3- [prjxray] mithro opened issue #1286: Instability in DSP timing fuzzer - https://git.io/Jv5JV | 00:05 | |
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| daniellimws | Working on a project using one of Xilinx's IP cores, is there a way in prjxray to run simulations on that core? Or I have no choice but to use Vivado's simulator | 01:17 |
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| litghost | Most hardblocks are missing simulation models right now | 01:35 |
| litghost | Adding simulation models is an open task | 01:35 |
| daniellimws | I suppose that it would take some effort to do that for each core? | 01:44 |
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| litghost | Not core, hardblock | 02:43 |
| litghost | So DSP, BRAM, PHASER_IN/OUT, PCIE | 02:44 |
| daniellimws | Oh in the case of the CORDIC IP that I am using now, it uses the PHASER_* block am I right? | 02:46 |
| daniellimws | So once a simulation model is built for the PHASER_IN/OUT hardblock, it is possible to simulate the CORDIC ips? Am I understanding this correctly? | 02:58 |
| litghost | Before that, we need to fuzz PHASER_IN/_OUT, which hasn't been done yet | 03:13 |
| litghost | So overall a lot of work | 03:13 |
| daniellimws | Oh dear | 03:39 |
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| -_whitenotifier-3- [yosys] rakeshm75 opened issue #66: Branch: Quicklogic : Functional issue in the design - https://git.io/Jv5GK | 06:55 | |
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| sf-slack | <r.jordans> Hi all, does anyone know what the current status of the soft-error-detection block for ECP5 is? I see that there is a SEDGA test in the fuzzers directory but I don't see anything yet in the database | 12:50 |
| daveshah | r.jordans: It isn't currently supported | 12:51 |
| sf-slack | <r.jordans> Anything I can do to get it supported? | 12:51 |
| daveshah | the main blocker is reverse engineering the CRC32 (in particular what exactly it is calculated over) inserted in the bitstream in SED mode | 12:51 |
| daveshah | the nextpnr changes to support the SED primitives are simpler and I am happy to do those once the CRC is sorted | 12:51 |
| sf-slack | <r.jordans> ok, so I guess that's the crc of the bitfile it compares against in the hardware? I guess that it's mainly the polynome that's missing? do we already have a way of getting some example crcs for different bitfiles? | 12:53 |
| daveshah | No, setting up something up to do that would be a first step | 12:53 |
| sf-slack | <r.jordans> ah, ok | 12:54 |
| sf-slack | <r.jordans> I don't have much experience with this but would like to see this working so I'll try to free up some time | 12:54 |
| sf-slack | <r.jordans> I did however do a bit of reverse engineering crc in the past though so hopefully that can help here | 12:55 |
| FFY00 | daveshah, what work has been done reverse engineering the crc? | 12:56 |
| daveshah | The normal CRC16 is fully RE'd its the BUYPASS algorithm | 12:57 |
| daveshah | I haven't looked at the SED CRC32 at all, but based on the CRC16 it's probably a standard algorithm | 12:57 |
| FFY00 | do you have samples? | 12:57 |
| daveshah | The hard part is probably working out what it is calculated over (and in what order) rather than the polynomial it uses | 12:57 |
| daveshah | No | 12:57 |
| FFY00 | yes, there aren't many well suited polynomials | 12:58 |
| FFY00 | well, if it is following the standard that shouldn't be an issue | 12:59 |
| daveshah | What standard? | 12:59 |
| FFY00 | the issue if finding the xor in, xor out, reflect in and reflect out | 12:59 |
| FFY00 | crc32 | 12:59 |
| daveshah | ah | 13:00 |
| FFY00 | 32 bits is a bit, but it could be bruteforced with some cleaver techniques | 13:00 |
| FFY00 | since crc is not really designed to be a protection mechanism | 13:01 |
| FFY00 | I was looking into this a few days ago | 13:01 |
| FFY00 | to reverse engineer the crc of a firmware I wanted to replace | 13:02 |
| FFY00 | this is an interesting read, if you have time: https://www.cosc.canterbury.ac.nz/greg.ewing/essays/CRC-Reverse-Engineering.html | 13:02 |
| tpb | Title: CRC Reverse Engineering (at www.cosc.canterbury.ac.nz) | 13:02 |
| FFY00 | how could I get samples? | 13:03 |
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| daveshah | FFY00: create some bitstreams using the SED function with Diamond | 13:19 |
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| daveshah | then look for the CRC32 following 0xA2 0x00 0x00 0x00 in the bitstream file | 13:20 |
| daveshah | in general, values in ECP5 are big endian so I expect that would apply here too | 13:20 |
| FFY00 | okay | 13:21 |
| FFY00 | I'll probably look into it when my ecp5 board arrives | 13:21 |
| FFY00 | or maybe before, we'll see | 13:24 |
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| -_whitenotifier-3- [symbiflow-arch-defs] acomodi opened issue #1390: fasm2frames has a high run-time with large designs - https://git.io/Jv5MV | 17:47 | |
| mithro | https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/1251/files?short_path=04c6e90#diff-04c6e90faac2675aa89e2176d2eec7d8 | 18:43 |
| tpb | Title: doc: Add optimization animations to readme by kmurray · Pull Request #1251 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 18:43 |
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