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| wallacejohn | ZirconiumX, mithro, hackerfoo: Thanks for the input on my first pull request; kmurray accepted it, and I've already submitted a second PR with more converted scripts. A couple of additional questions: | 01:07 |
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| wallacejohn | I found Issue #16 under SymbiFlow/ideas (convert VtR Perl scripts to Python) and am interested in taking this on after finishing the 2to3 conversions. It looks like this issue hasn't been mentioned in almost two years -- is this still an active/relevant issue? | 01:07 |
| wallacejohn | Also, I'm considering submitting a proposal for a GSoC project with you guys and am interested in SymbiFlow/ideas Issue #18 (Python BLIF/eBLIF library). Same question -- is this still relevant after two years of inactivity? Is the scope of this issue reasonable for a GSoC summer project? | 01:08 |
| mithro | wallacejohn: Great work! | 01:08 |
| mithro | wallacejohn: The Python BLIF / eBLIF library is still *currently* relevant, but it might become less relevant if our work on the Capn'Proto file format happens | 01:09 |
| mithro | wallacejohn: You are also welcome to propose your own ideas / projects -- the most successful students tend to be the ones who take the time to find something they are super excited to build and just happens to also fit something we are interested in. | 01:11 |
| mithro | wallacejohn: Did you find https://symbiflow.github.io/summer-of-code ? | 01:11 |
| tpb | Title: SymbiFlow - the GCC of FPGAs (at symbiflow.github.io) | 01:11 |
| mithro | wallacejohn: You might also want to talk to kgugala about the vtr-flow conversion idea -- I believe they were working on doing a distributed version of it at https://github.com/antmicro/vtr-flow-distant | 01:13 |
| tpb | Title: GitHub - antmicro/vtr-flow-distant (at github.com) | 01:13 |
| mithro | https://github.com/antmicro/distant-rec#verilog-to-routing | 01:15 |
| tpb | Title: GitHub - antmicro/distant-rec (at github.com) | 01:15 |
| mithro | wallacejohn: Also updated an existing issue with more content / links / etc is always a good idea | 01:16 |
| mithro | wallacejohn: If your interest is file formats -- you might also be interested in https://docs.google.com/document/d/143ZHhMqAlA5EeVYRP6dUGUZJtsfgbZv_cC-wqvKeOcI/edit | 01:19 |
| tpb | Title: FPGA Tooling Common Interchange Formats - Google Docs (at docs.google.com) | 01:19 |
| wallacejohn | mithro: Thanks for the links; yes, I found the SymbiFlow GSoC page. I have a wide array of interests and generally find it more difficult to narrow my focus, so I figured the ideas page would be a good place to start. I'll spend some time exploring those links. I do find file/data formats pretty interesting and would like to get involved in a related project as a means to learn more about the topic. | 01:44 |
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| musazal | Hope you are all doing fine. I'm a third year Electrical Engineering student with interest in Computer Architecture and RISCV. Previously, I've done made a custom RV32I core in verilog for the last summer project and I'm interested in adding the f-extension. For now, I'm trying to work in SystemVerilog so that it can be moved further towards | 09:02 |
| musazal | verification. So, is there any project for GSoC that I can take part in keeping in mind background that I currently have. Any advice will be really appreciated. | 09:02 |
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| sf-slack | <adityasaini70> Hello everyone ! I'm an Electronics and Communication sophomore at IIITD, India. I'm familiar with Xilinx 7series FPGA architecture and have done a couple of projects with the Xilinx Artix-7 development board. I'm a GSOC aspirant and I wanted to talk about contributing to Project X-Ray. Can anybody help ?? | 11:40 |
| ZirconiumX | adityasaini70: hello, I can try my best | 12:51 |
| ZirconiumX | If you go back through the logs, there have been a fair few ideas thrown around, but it's important to note that there is much more to Symbiflow than just prjxray | 12:53 |
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| clay_1 | Good morning everyone ! | 14:03 |
| Degi | I've written a rough summary for the ECP5 PCIe https://github.com/x44203/ECP5-PCIe | 14:03 |
| tpb | Title: GitHub - x44203/ECP5-PCIe: ECP5 to PCIe interface development (at github.com) | 14:03 |
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| hackerfoo | Good morning | 16:11 |
| sf-slack | <acomodi> :q | 16:18 |
| sf-slack | <acomodi> Sorry, wrong window | 16:18 |
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| -_whitenotifier-3- [symbiflow.github.io] mithro opened issue #3: Broken link to student guide on Summer of Code page - https://git.io/Jv1NU | 19:14 | |
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| mithro | QotD: "The syntax diagnostics from the compiler made by Sue Graham's group at Berkeley were the most helpful I have ever seen - and they were generated automatically. At a syntax error the compiler would suggest a token that could be inserted that would allow parsing to proceed further. No attempt was made to explain what was wrong. The compiler taught me Pascal in an evening, with no manual at hand." -- Doug McIlroy - | 20:24 |
| mithro | https://minnie.tuhs.org/pipermail/tuhs/2020-March/020664.html | 20:24 |
| tpb | Title: [TUHS] The most surprising Unix programs (at minnie.tuhs.org) | 20:24 |
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| lambda | daveshah: when trying to pnr litedram, I get "ERROR: IDELAYE2 'dram.litedram_inst.IDELAYE2' has IDATAIN input connected to illegal cell type IOBUF" - which, to be fair, it is, but I'm assuming that's supposed to legal or it wouldn't work for anyone. | 23:49 |
| daveshah | lambda: it sounds like the IOBUF isn't being split properly | 23:50 |
| daveshah | I'll take a look tomorrow if you can provide a netlist | 23:51 |
| lambda | daveshah: sure thing, thanks a lot :) | 23:52 |
| daveshah | I guess this comes from the most recent litedram change to make DQS inout | 23:52 |
| lambda | the signal in question it's complaining about is dq[0], but it'll probably be the same for dqs then | 23:54 |
| daveshah | Oh no it won't be from that then, no idea what it would be | 23:55 |
| lambda | (rebuilding with latest litedram right now) | 23:57 |
| daveshah | I'm pretty sure this is a Yosys or nextpnr issue | 23:58 |
| lambda | even if, I don't want to be the one bothering people about bugs that are already fixed ;) | 23:59 |
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