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| hackerfoo | Is there a way to use VPR to translate a capnproto rr_graph to XML? | 00:46 |
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| litghost | Of course | 00:49 |
| litghost | The read/write arguments support both XML and capnp | 00:49 |
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| sf-slack | <acomodi> Got the minilitex_ddr test to work at 100MHz | 15:36 |
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| litghost | acomodi: Nice, what needed to be changed? | 17:02 |
| litghost | acomodi: Did vivado report timing closure? | 17:02 |
| litghost | acomodi: I assume you mean the design in https://github.com/SymbiFlow/symbiflow-arch-defs/pull/1320 ? | 17:03 |
| tpb | Title: WIP: Add Base Litex minitest capable of running Linux on Vexriscv by tmichalak · Pull Request #1320 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 17:03 |
| sf-slack | <acomodi> @litghost Exactly, so, by using the same clock for CLKB and CLK in ISERDESes seems to have solved the problem. There is to say though that both Vivado and VPR do report timing violations, but the design works on HW | 17:07 |
| litghost | acomodi: How large is the violation? I expect a ~0.5 ns setup slack violation is fine, but a 2-4 ns setup violation or a 1-2 ns hold violation likely eats away most of the timing models margin | 17:09 |
| sf-slack | <acomodi> litghost: regarding VPR there is only a setup violation of -3.776 ns | 17:15 |
| litghost | acomodi: Yikes, that is pretty substantial. Vivado will likely report an even large setup violation, I'd guess ~4 ns. With a setup violation of that magnitude against a target CPD of 10 ns, I'd expect that bitstream to fail on a measureable number of parts | 17:18 |
| sf-slack | <acomodi> litghost: and a worst setup violation of -8.081 ns | 17:18 |
| litghost | acomodi: For now I recommend we leave the SDC at 50 MHz, and create an issue to track getting timing closure at 100 MHz for future work | 17:18 |
| sf-slack | <acomodi> litghost: the interesting part is that the implementation behaves as it should on HW | 17:18 |
| sf-slack | <acomodi> litghost: sure, I can revert to 50MHz | 17:19 |
| litghost | acomodi: Of course. The timing model is typically very conservative so that it works on the full distribution of parts that come out of manufacturing. However if you were to deploy that same bitstream over 100 to 1000 parts, I'd expect a non-trival number of them to fail | 17:19 |
| litghost | acomodi: I don't have a good intuition on the histrogram of part quality. | 17:20 |
| sf-slack | <acomodi> litghost: makes sense. Well, once we get everything stable and merged, we can focus on further improve the timing model, as suggested | 17:21 |
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| hackerfoo | There are far too few assertions in VPR. | 18:25 |
| litghost | hackerfoo: VPR provides way to have varying levels of assertions, and the upstream maintainers will likely accept PR's to that affect | 18:26 |
| hackerfoo | I found at least one bug in the serializer that requires ptcs to be ordered. | 18:27 |
| hackerfoo | We need fuzzing, too. | 18:28 |
| litghost | hackerfoo: I assume you are refering to something in https://github.com/SymbiFlow/vtr-verilog-to-routing/blob/master%2Bwip/vpr/src/route/rr_graph_uxsdcxx_serializer.h#L1700 ? | 18:33 |
| tpb | Title: vtr-verilog-to-routing/rr_graph_uxsdcxx_serializer.h at master+wip · SymbiFlow/vtr-verilog-to-routing · GitHub (at github.com) | 18:33 |
| hackerfoo | https://github.com/SymbiFlow/vtr-verilog-to-routing/blob/master%2Bwip/vpr/src/route/rr_graph_uxsdcxx_serializer.h#L1740-L1758 | 18:34 |
| tpb | Title: vtr-verilog-to-routing/rr_graph_uxsdcxx_serializer.h at master+wip · SymbiFlow/vtr-verilog-to-routing · GitHub (at github.com) | 18:34 |
| hackerfoo | push_back | 18:34 |
| hackerfoo | I should have a PR today or tomorrow. | 18:34 |
| litghost | hackerfoo: Ya that code is terrible, and has been terrible since forever | 18:35 |
| hackerfoo | But segment order also seems to be assumed, so I have to fix that. | 18:35 |
| litghost | hackerfoo: PTC's are poorly documented, and aren't used often either :/ | 18:35 |
| litghost | hackerfoo: Segment order should be soley determined by the id attribute? | 18:36 |
| litghost | hackerfoo: When generated it is implicit, but the serializer should always be key'd on "id" | 18:36 |
| hackerfoo | Something's breaking the segment_map_ in connection_box_lookahead, at least. | 18:37 |
| litghost | hackerfoo: An inconsistent lookahead binary could have different segment definitions from the rrgraph segments. But the rrgraph segments should be fixed once the virtual rr graph is generated | 18:39 |
| litghost | hackerfoo: And the crude caching system we have should detect a change in the input patched rrgraph, even segment definitions, and recompute the lookaheah | 18:39 |
| hackerfoo | Thanks. I'll look into that. | 18:41 |
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| hackerfoo | Recomputing the segment map takes 0.01 seconds. I'm removing it from the lookahead bin file. | 19:04 |
| litghost | ok | 19:07 |
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| -_whitenotifier-3- [yosys-symbiflow-plugins] litghost opened issue #8: Assertion violation in XDC plugin - https://git.io/JvBR0 | 19:39 | |
| hackerfoo | litghost: https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/1162 | 20:21 |
| tpb | Title: Fix Serialization of ptcs by HackerFoo · Pull Request #1162 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 20:21 |
| hackerfoo | https://github.com/SymbiFlow/vtr-verilog-to-routing/pull/412 | 20:55 |
| tpb | Title: Remove cached segment map from connection map lookahead file. by HackerFoo · Pull Request #412 · SymbiFlow/vtr-verilog-to-routing · GitHub (at github.com) | 20:55 |
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| -_whitenotifier-3- [prjxray] litghost opened issue #1248: Refactor xjson library - https://git.io/JvBaC | 23:13 | |
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