Tuesday, 2020-02-04

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mithromkurc: For the changes to v2x - can you make sure they updated the documentation at https://python-symbiflow-v2x.readthedocs.io/en/latest/index.html?11:37
tpbTitle: Welcome to SymbiFlow Verilog to XML SymbiFlow Verilog to XML (V2X) 0.0-410-g4898bf6 documentation (at python-symbiflow-v2x.readthedocs.io)11:37
sf-slack<mkurc> @mithro Ok, I'll update the docs.11:38
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-_whitenotifier-3- [prjxray] mithro opened issue #1219: 005-tilegrid failing on Zynq - https://git.io/JvGRL11:45
mithroacomodi: It looks like the tilegrid fuzzer is failing on zynq? - https://github.com/SymbiFlow/prjxray/issues/121911:45
tpbTitle: 005-tilegrid failing on Zynq · Issue #1219 · SymbiFlow/prjxray · GitHub (at github.com)11:45
sf-slack<acomodi> @mithro: Hmm, this is unexpected, the question is why it is failing now? Is there a full log somewhere? I wonder whether this is related to the extra-part zynq010 or the zynq02011:48
mithroacomodi: I put them in the github issue just then11:50
sf-slack<acomodi> mithro: great, thanks11:50
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mithroacomodi: Regarding the clock inversion12:04
mithroacomodi: https://github.com/antmicro/prjxray/commit/2d13b11f1350667d8536dc0e80daa995e1d72e7212:04
tpbTitle: Merge pull request #935 from litghost/more_ilogic_bits · antmicro/prjxray@2d13b11 · GitHub (at github.com)12:04
mithroacomodi: So IS_CLKB_INVERTED is never generated?12:07
mithro`~/github/SymbiFlow/prjxray/database$ grep -R IS_CLKB_INVERTED` returns nothing...12:08
sf-slack<acomodi> @mithro: exactly, as far as I have seen, by setting or unsetting the IS_CLKB_INVERTED, no bit is changing12:08
sf-slack<acomodi> And, as a result, we lack the IS_CLKB_INVERTED feature12:09
mithroacomodi: I think IS_CLKB_INVERTED is actually *implied* by the mode the serdes is being used in?12:10
mithroacomodi: https://forums.xilinx.com/t5/Implementation/IS-CLK-INVERTED-attribute-of-ISERDES/m-p/992062/highlight/true#M2529912:11
tpbTitle: Re: IS_CLK_INVERTED attribute of ISERDES - Community Forums (at forums.xilinx.com)12:11
sf-slack<acomodi> mithro: well, this tan explains the reason why we do not see any changes in the bits, I suppose. The problem now is, how to disable this implication? `MEMORY_QDR` interface type seems to be available only when using the MIG tool: https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf page 15312:17
mithrohttps://usercontent.irccloud-cdn.com/file/Io4AU8RF/Screenshot%20from%202020-02-04%2013-15-58.png12:17
mithroacomodi: I think the inverter should be absorbed into the ISERDES primitive...12:18
mithroActually...12:19
mithroWait - how is the MCMM configured?12:19
sf-slack<acomodi> You mean the PLL?12:19
mithroYeah12:19
mithroacomodi: It's generating CLK and ~CLK right?12:19
sf-slack<acomodi> No, it is generating a SYS_CLK, a SYS4x_CLK (fast clock for the IOSERDESes), a 90 degrees phased SYS4x_CLK12:21
mithrohttps://www.irccloud.com/pastebin/iObUbZ3U/12:23
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)12:23
sf-slack<acomodi> mithro: Could it be possible that, if this CLKB inverted is absorbed in the ISERDES primitive (and always active) we are feeding to the CLKB pin an inverted clock which is than inverted again by the pin inverter?12:23
mithrohttps://www.irccloud.com/pastebin/dFzqVXJD/12:24
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)12:24
sf-slack<acomodi> mithro: That bufg is necessary as, without it, the ~CLK would have been negated incorrectly without even passing through a BUFG12:26
mithroacomodi: Did you modify the generated verilog at all?12:27
sf-slack<acomodi> mithro: yes, but before that I have used Vivado to test it was correctly functioning. Apart from this we needed to add the OBUFs manually and the PLL phasing (90000 instead of 90)12:29
mithroCan you provide the diff?12:30
sf-slack<acomodi> Sure12:30
sf-slack<acomodi> mithro: https://pastebin.com/hbbiPhhL12:32
tpbTitle: 23,24c23 < output ddram_reset_n, < output [3:0] led --- > output ddram_re - Pastebin.com (at pastebin.com)12:32
mithroacomodi: Can you use unified diff output?12:34
sf-slack<acomodi> mithro: here it is https://pastebin.com/mCWHStjf12:36
tpbTitle: --- ddr_uart.v 2020-02-04 13:26:04.860069367 +0100 +++ ../../../../prjxray/mini - Pastebin.com (at pastebin.com)12:36
mithroacomodi: So the - lines are actually the ones you added?12:37
sf-slack<acomodi> mithro: yes, @mkurc has dealt with the OBUF issues12:39
sf-slack<acomodi> And this is applied also for the minilitex_ddr_test12:39
mithroacomodi: This change doesn't look right12:41
mithroacomodi: In the original source, the sys4x_clk signal was set up to drive CLK and CLKB but you changed CLKB to be ~sys4x_clk?12:46
sf-slack<acomodi> Oh, actually I've sent you a wrong diff as I am currently changing the design to see whether, by leaving CLKB equal to CLK, things get to work. Anyway, the original source has CLKB equal to `~sys4x_clk`  and CLK to `sys4x_clk`12:50
mithroacomodi: Which comes from https://github.com/enjoy-digital/litedram/blob/74f72f91a03156cfa23b7615dabd81c858d0b933/litedram/phy/s7ddrphy.py#L429-L430 ?12:51
tpbTitle: litedram/s7ddrphy.py at 74f72f91a03156cfa23b7615dabd81c858d0b933 · enjoy-digital/litedram · GitHub (at github.com)12:51
sf-slack<acomodi> mithro: yes, should be that one12:52
mithro_florent_: You got a moment for a question about the clocking of the ISERDES in Artix-7 parts?12:54
sf-slack<acomodi> mithro: this is the current correct diff in the uart-ddr PR: https://pastebin.com/9W4Ffe0q12:56
tpbTitle: --- ddr_uart.v 2020-02-04 13:52:01.455432878 +0100 +++ /home/alessandro/project - Pastebin.com (at pastebin.com)12:56
_florent_mithro: yes13:05
mithro_florent_: So in the ISERDES2 at https://github.com/enjoy-digital/litedram/blob/74f72f91a03156cfa23b7615dabd81c858d0b933/litedram/phy/s7ddrphy.py#L429-L430 you drive i_CLK with ddr_clk and i_CLKB with ~ddr_clk -- what is the expected outcome in Vivado?13:08
tpbTitle: litedram/s7ddrphy.py at 74f72f91a03156cfa23b7615dabd81c858d0b933 · enjoy-digital/litedram · GitHub (at github.com)13:08
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mithromkurc: When writing the README.rst you should be describing the feature that is being tested rather than the bug itself13:16
sf-slack<mkurc> @mithro: Right, I'll make them more focused on the feature.13:17
mithromkurc: https://python-symbiflow-v2x.readthedocs.io/en/latest/tests/dsp/dsp_combinational.html13:17
tpbTitle: dsp_combinational test SymbiFlow Verilog to XML (V2X) 0.0-410-g4898bf6 documentation (at python-symbiflow-v2x.readthedocs.io)13:17
_florent_mithro: from UG471: "The high-speed secondary clock input (CLKB) is used to clock in the input serial data stream. In any mode other than MEMORY_QDR, connect CLKB to an inverted version of CLK."13:17
mithro_florent_: Let me rephrase -- How do you expect the inverted ddr_clk be generated?13:18
mithro_florent_: IE I would expect you would need to use the PLL to generate a 180 degree shifted ddr_clk ?13:20
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_florent_mithro: i'm not sure since it's possible there is a hardware inverted directly in the ISERDESE213:24
_florent_mithro: on Ultrascale, i'm sure there is a hardware inverted on CLKB and you have parameter to specify the behaviour13:25
_florent_mithro: i would need to look for 7-Series13:25
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_florent_mithro: it also seems to be used like that on others designs:13:28
_florent_https://github.com/LBL-BIDS/fpga-family/blob/24d4df6d5ca62e078b4663cbdc7557ee0693f0e8/iserdes/lvds_iophy.v#L3213:28
tpbTitle: fpga-family/lvds_iophy.v at 24d4df6d5ca62e078b4663cbdc7557ee0693f0e8 · LBL-BIDS/fpga-family · GitHub (at github.com)13:28
_florent_https://github.com/Blackieyan/AD9653_DAC3484/blob/40df90dd0cc775e85fd6948b134ba87e29f5df59/project_missle.srcs/sources_1/ad/Frame_Check.v#L8313:29
tpbTitle: AD9653_DAC3484/Frame_Check.v at 40df90dd0cc775e85fd6948b134ba87e29f5df59 · Blackieyan/AD9653_DAC3484 · GitHub (at github.com)13:29
mithroThis image seems to imply that the CLK / CLKB have inverters https://usercontent.irccloud-cdn.com/file/DEQ3mfci/image.png13:30
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sf-slack<acomodi> @mithro: I have tried to feed the same clock to both CLK and CLKB to ISERDESes, and the whole design passed through fasm2bels with no errors. There is no diff in the FASM files and, by inspecting the resulting .dcp, the CLKB inverter is enabled.14:53
sf-slack<acomodi> Still, the design does not work on HW, I guess still for hold/setup violations14:54
mithroacomodi: Okay, so Yosys should absorb the inverter into the ISERDES then I guess?14:54
mithroacomodi: Does it work with Yosys->Vivado and FASM2BELs?14:54
sf-slack<acomodi> mithro: Actually I am quite unsure of what happens there. By inspecting fasm2bels, the IS_CLKB_INVERTED parameter is added to the resulting verilog. I am not sure this is a Yosys doing. This inverter seems to be working in a pretty strange way. By setting or unsetting in the verilog instantiation, nothing changes)15:01
sf-slack<acomodi> mithro: I need to check that15:01
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Xiretzadaveshah: route failure from SITEWIRE/SLICE_X7Y94/C6LUT_O6 to SITEWIRE/SLICE_X2Y97/CEUSEDMUX_OUT with f49d299, I can give you the json and xdc in a sec19:17
daveshahThanks, I will look tomorrow. I think this is probably another shift register issue19:18
Xiretzadaveshah: oh, somehow my -nosrl got lost, will retry with that19:19
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Xiretzayep, seems like it, router starts fine with -nosrl. anyway, here's the files: https://misc.xiretza.xyz/repro/f49d299b_route_fail.tar.gz19:23
daveshahThanks!19:26
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Xiretzahuh, another interesting problem: just updated yosys (I'm assuming that's what's the problem), now router2 is stuck at overused=147 and it's not going down any further.20:02
litghostXirertza: What part are you targetting?20:03
Xiretzalitghost: xc7a35tcsg32420:04
Xiretzait worked a moment ago and the only thing that changed is yosys, I'll downgrade that and try again20:05
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Xiretzayeah, that's it, specifically 34d2fbd2 "Add opt_lut_ins pass". I'll hop on over to #yosys then20:14
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