Sunday, 2020-02-02

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ricosI'd like to use nextpnr-xilinx with an artix7 and an ISERDESE2 (see https://pastebin.com/f8u1cCnP ). Unfortunately nextpnr-xilinx crashes with https://pastebin.com/xT4xPgDt . How could I get that working?12:09
tpbTitle: [VeriLog] `default_nettype none module top (input clk, output [7:0] LED_o, input pio3, - Pastebin.com (at pastebin.com)12:09
ZirconiumXdaveshah: ^12:23
daveshahricos: what Yosys version and script are you using?12:25
ricosdaveshah Yosys 0.9+932 (git sha1 342d91f, clang 9.0.0 -fPIC -Os)12:26
ricosyosys -p "synth_xilinx -flatten -abc9 -nobram -arch xc7 -top top; write_json cmod.json" top.v12:26
ricosI'm not exactly sure what you mean with "script". Is that just the command line or anything else?12:32
daveshahYes, the script is the bit in -p12:32
daveshahI would recommend a newer Yosys. Older Yosys didn't do IO buffer insertion, and the IO buffer insertion in nextpnr isn't perfect12:33
daveshah(can't immediately find where 342d91f comes from, but +932 is quite a bit older than +1706 I have here)12:34
ricosok, let me try ...12:35
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ricosdaveshah, somehow the sha1 is broken here, tried with Yosys 0.9+1706 (git sha1 342d91f, clang 9.0.1 -fPIC -Os)13:19
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ricosdaveshah, got E"RROR: JSON module whitebox attribute value is not a number" now13:21
daveshahricos: I think I pushed a fix for that to nextpnr-xilinx yesterday13:31
ricosdaveshah: with nextpnr-xilinx (6d80688) I now get terminate called after throwing an instance of 'std::invalid_argument'13:36
ricosprobably need to update prjxray ...13:37
daveshahDepending on when you last built it, more important is probably just rebuilding the bba/bin13:41
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ricosdaveshah, it is still an issue but now https://pastebin.com/tN3STdQS14:07
tpbTitle: no dangling wires. checking net $auto$clkbufmap.cc:247:execute$278 driver: - Pastebin.com (at pastebin.com)14:07
daveshahMight be an issue with the way you are using the ISERDES. Only a limited set of configs have been tested14:08
ricosdo you know which one where tested?14:09
daveshahPrimarily what litedram (https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/s7ddrphy.py) uses14:10
tpbTitle: litedram/s7ddrphy.py at master · enjoy-digital/litedram · GitHub (at github.com)14:10
daveshahCan you post your design somewhere? I can see if it would be possible to get it working with the current state of prjxray14:10
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ricosdaveshah, the design is here https://pastebin.com/f8u1cCnP not sure if it should work at all...14:14
tpbTitle: [VeriLog] `default_nettype none module top (input clk, output [7:0] LED_o, input pio3, - Pastebin.com (at pastebin.com)14:14
daveshahIS_CLK_INVERTED("FALSE") should be (0)14:14
daveshah(I need to work on a better error for this)14:15
daveshah7:1 mode hasn't been tested yet, I can't guarantee that it will work14:15
ricosshould the 0 used for all IS_* ?14:16
daveshahYes14:16
ricoshence this worked :-)14:17
ricosno crash, but it found no clocks14:19
daveshahThat's fine, it doesn't do timing analysis of SERDES atm14:19
ricosok14:19
ricosdaveshah, thanks for your help14:28
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Xiretzadaveshah: I know timing isn't very accurate yet, but I'm getting 20%+ higher fmax on :xilinx than on :router2, is that expected?18:45
daveshahYes, it's possible, router2 is optimised more for runtime than fmax at the moment18:46
daveshahusually it's less than 10% different but an edge case is always possible18:47
Xiretzaah, interesting18:47
daveshahthe inaccuracies in timing analysis might not be helping either18:47
daveshahIn the long run, when it has timing-driven rip up, router2 should also be able to give better timing (at the expense of runtime) for some trickier constraintsd18:48
Xiretzanice, at the moment I don't have any timing concerns anyway, was just surprised to see such high numbers after updating everything18:50
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