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| Xiretza | daveshah: nextpnr-xilinx routing has become incredibly slow, basically not finishing at all for anything larger than a few gates, is that known? | 09:05 |
|---|---|---|
| daveshah | Xiretza: there was a change relating to some IO but it shouldn't add more than a second or so | 09:06 |
| daveshah | Have you rebuilt the database after updating? | 09:06 |
| Xiretza | daveshah: prjxray/database hasn't updated since december, but I did rerun bbaexport/bbasm, yes | 09:08 |
| daveshah | Yeah that's what I was checking | 09:09 |
| daveshah | attosoc.sh still routes fine for me, about 18s which is similar to before | 09:09 |
| daveshah | You can try the router2 branch, that is a new experiemental router that is usually much faster | 09:10 |
| Xiretza | daveshah: I did try that, but it errored because it couldn't find a route - maybe I just hadn't rebuilt the db though, will try that now | 09:13 |
| daveshah | If it hits an error then that needs to be looked into - router2 will be the default for xilinx very soon | 09:14 |
| Xiretza | daveshah: router2 managed to route one design now, but another (that didn't ever finish with latest xilinx branch) gives "Failed to route arc 0 of net [...]". | 09:21 |
| daveshah | Can you post the design? | 09:22 |
| daveshah | also, curious how quickly did old nextpnr route it? how big is it? | 09:22 |
| Xiretza | it's just the IO part of a UART (state machine, shift registers, parity), so not very | 09:23 |
| daveshah | My guess is that somehow the design is being placed in an unrouteable way | 09:24 |
| Xiretza | what would you like, write_verilog output, json? the actual sources are VHDL | 09:24 |
| daveshah | json and xdc | 09:24 |
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| Xiretza | daveshah: http://misc.xiretza.xyz/router2_failed_to_route.tar.gz | 09:39 |
| daveshah | Xiretza: thanks, I can reproduce the bug | 09:47 |
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| daveshah | Yup, it's a random placer bug as thought | 09:50 |
| daveshah | Xiretza: fix pushed | 09:57 |
| Xiretza | daveshah: great, it works! | 10:31 |
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| hackerfoo | Do we have something like DRCs yet? Would it be worth adding some checks for clock routing? | 21:51 |
| hackerfoo | I know we have fasm2v, but it still might be worth adding our own checks. | 21:52 |
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