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| -_whitenotifier-5- [prjxray] mkurc-ant opened issue #1183: Possible instability of 047 for Zynq - https://git.io/Je5fi | 09:22 | |
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| flow | Thank you for the amazing work! I just tried to build the LiteX SoC for one of my boards, the resulting bitstream is larger (693,607 vs 582,343 bytes) than the bitstream size I get when synthesizing my other designs (which are a lot less ambitious) might that be due to the ROM initialization? For my uploading tools I would prefer that the size of | 15:00 |
|---|---|---|
| flow | the bitstream is always fixed. Is there a way to force ecppack to initialize everything that is not used to 0 or some other value? | 15:00 |
| sf-slack | <kgugala> hi @flow which FPGA are you targeting? | 15:06 |
| flow | the ecp5 with 25k logic elements | 15:07 |
| flow | LFE5U-25F-6BG256C | 15:07 |
| daveshah | Yes, this is because of initialised RAM | 15:09 |
| daveshah | There is no option like that at present | 15:09 |
| daveshah | But you can safely pad bitstreams with 0xFF at the end if that helps | 15:09 |
| flow | oh thats good to know and fixes my problem, Thank you! | 15:09 |
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| hackerfoo | Interesting. Hyper-registers are pulse latches: http://kalman.mee.tcd.ie/fpl2018/content/pdfs/FPL2018-43iDzVTplcpussvbfIaaHz/1PNSl54xKC7BAFw7YOeZRT/1sc2uahgEryvvJ7qQkPXkz.pdf (pg2), https://www.eetimes.com/pulse-latch-approach-reduces-dynamic-power | 21:20 |
| hackerfoo | Has anyone seen an error like this? make[4]: *** No rule to make target '../xc7/archs/artix7/devices/xc7a50t-virt/xsltproc', needed by 'xc7/archs/artix7/devices/xc7a50t-virt/arch.merged.xml'. Stop. | 21:33 |
| hackerfoo | `make all_conda` doesn't help. | 21:34 |
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| -_whitenotifier-5- [symbiflow-arch-defs] rodrigomelo9 opened issue #1243: parse_pdf_modules.py seems to be not working - https://git.io/Je5lX | 22:53 | |
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