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| -_whitenotifier-f- [python-symbiflow-v2x] kgugala opened issue #17: V2X cannot handle directly assigned wires - https://git.io/Je25f | 11:26 | |
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| mithro | tmichalak: https://github.com/SymbiFlow/yosys/pull/44/files looks way better than I expected! | 14:53 |
|---|---|---|
| tpb | Title: WIP: Initial version of the xdc plugin support by tmichalak · Pull Request #44 · SymbiFlow/yosys · GitHub (at github.com) | 14:53 |
| sf-slack | <tmichalak> @mithro: good to hear that. If this is the direction we want to go in I will proceed with merging this into symbiflow-arch-defs | 15:21 |
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| sf-slack | <stamatis_poulios> Hi all! I have recently discovered SymbiFlow and I'm kinda excited cause it seems very tempting. I would like to help with the projects, though I can't tell what I should start studying and/or where I could fit. I am currently reading the Docs to get an idea about how it works. Any advice will be apperciated. Thank you in advance! | 17:35 |
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| litghost | stamatis_poulios: What's your skill set and interest? We have work in python, verilog, C++, and "visualizations" (language TBD) | 18:42 |
| sf-slack | <stamatis_poulios> Thank you @litghost. I have more experience in HDL (VHDL/SystemVerilog), due to work done on MSc and PhD studies. Currently, I am working as embedded linux engineer (mostly writing applications in C++). Generally speaking, I would preferably work on HDL code. | 19:18 |
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| litghost | stamatis_poulios: We do not currently have much going on with VHDL at the moment. One area you might be able to help with, but I know less about, is our open source SystemVerilog work. I know we are building up a SystemVerilog standard verification suite, and adding more parts of the standard, especially bits that are high value but missing, is of value. | 19:20 |
| litghost | stamatis_poulios: On the pure Verilog front, we need more testbenchs and test circuits for symbiflow-arch-defs to test that things work in simulation and hardware as expected | 19:21 |
| litghost | SystemVerilog test suite is here: https://github.com/SymbiFlow/sv-tests | 19:22 |
| tpb | Title: GitHub - SymbiFlow/sv-tests: Test suite designed to check compliance with the SystemVerilog standard. (at github.com) | 19:22 |
| sf-slack | <stamatis_poulios> Thank you very much guys. I will check what you proposed, to see how I could contribute. | 19:40 |
| -_whitenotifier-f- [vtr-verilog-to-routing] litghost opened issue #313: Branch: fix_cache_of_timing_info - https://git.io/JeaLO | 23:11 | |
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