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| sf-slack | <jake.mercer> Am I on the right track with this? Or am I missing something? `make run` is able to complete without any DRC violations or other errors. The blurb associated with the A_INPUT attribute is: ""DIRECT" Selects the input to the A port between parallel input ("DIRECT") or the cascaded input from the previous slice ("CASCADE")." I have assumed "DIRECT" is 0 and "CASCADE" is 1 in generate.py, is there any way to know | 02:51 |
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| sf-slack | for sure? | 02:51 |
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| sf-slack | <mkurc> @jake.mercer The truth is that you can't be 100% sure that the parameter you are changing is correlated with a bit in the bitstream. In your case Vivado may not enable the CASCADE frature if you don't connect the other DSP cell in the cascade chain. | 07:04 |
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| sf-slack | <jake.mercer> Gotcha, so it's mostly a case of try it in various configurations/nets and see what works | 11:32 |
| mithro | jake.mercer: While you waiting for the fuzzers to run, you could start working on a sim model | 11:40 |
| sf-slack | <jake.mercer> Where are they in the tree? Is there an example I can look at? | 12:47 |
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| daveshah | jake.mercer: There's a DSP48E1 model in Yosys that I was working on that might be useful | 14:35 |
| daveshah | https://github.com/YosysHQ/yosys/blob/xc7dsp/techlibs/xilinx/cells_sim.v#L529 | 14:35 |
| tpb | Title: yosys/cells_sim.v at xc7dsp · YosysHQ/yosys · GitHub (at github.com) | 14:35 |
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| sf-slack | <jake.mercer> Thanks:) | 17:16 |
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