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| hackerfoo | Getting closer. I was able to generate rr_graph.real.xml. Now I need to fix this: PCF constraint "set_io in[0] V17" from line 2 constraints net in[0] which is not in available netlist: in, out | 01:42 |
|---|---|---|
| hackerfoo | Hopefully not too much more to go. | 01:43 |
| hackerfoo | V17 isn't one of the pins I selected (W2/3 & V2/3) | 01:43 |
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| litghost | hackerfoo: What target are you running | 15:55 |
| litghost | hackerfoo: The current process is sdc -> ioplace | 15:55 |
| litghost | pcf* | 15:55 |
| litghost | https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc7/make/arch_define.cmake#L45 | 15:57 |
| tpb | Title: symbiflow-arch-defs/arch_define.cmake at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 15:57 |
| hackerfoo | litghost: buttons_basys3_x1y0_fasm | 15:59 |
| litghost | hackerfoo: Did you update basys3.pcf? | 16:04 |
| litghost | Or make a new pcf for the x1y0 test? | 16:05 |
| hackerfoo | Yeah | 16:05 |
| litghost | Which? And did you update the CMake description of the test to use the correct file? | 16:06 |
| hackerfoo | I just modified the existing one. I'll make a separate one when it works. | 16:10 |
| litghost | hackerfoo: The error matches the pcf file located in master (https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc7/tests/buttons/basys3.pcf) | 16:11 |
| tpb | Title: symbiflow-arch-defs/basys3.pcf at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 16:11 |
| litghost | hackerfoo: Which path did you edit? | 16:12 |
| hackerfoo | That was before I modified the PCF. | 16:12 |
| litghost | Ah, sure | 16:13 |
| hackerfoo | Still fails the same way, though. | 16:13 |
| hackerfoo | The netlist is missing from the eblif, I think. | 16:13 |
| hackerfoo | Or net. | 16:13 |
| litghost | hackerfoo: I'm guess, but I think it's because the new design no longer has a bus | 16:15 |
| litghost | hackerfoo: e.g. input [0:0] in -> set X in, versus input [1:0] in -> set X in[0] | 16:16 |
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| hackerfoo | I see | 17:28 |
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| hackerfoo | Now the pads are missing from synth_tiles_pinmap.csv | 19:46 |
| hackerfoo | I think I need to add a way of locating real pads, because they were previously synthetic tiles. | 19:53 |
| hackerfoo | Maybe I can still add them to synth_tiles.json | 19:54 |
| litghost | hackerfoo: You looking for https://github.com/SymbiFlow/prjxray-db/blob/master/artix7/xc7a35tcpg236-1_package_pins.csv by any chance? | 20:10 |
| tpb | Title: prjxray-db/xc7a35tcpg236-1_package_pins.csv at master · SymbiFlow/prjxray-db · GitHub (at github.com) | 20:10 |
| hackerfoo | litghost: Thanks, that looks useful. | 20:11 |
| hackerfoo | I'm adding code to prjxray_create_synth_tiles.py to add an entry for each IOPAD, similar to GND & VCC. | 20:12 |
| hackerfoo | I should probably just try changing the JSON manually first. | 20:13 |
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| hzeller[m] | While at it, I might be interested in U2, U4, U5, U7, U8, V4, V5, V7, V8, W4, W6, W7 :) (7-segment things in Basys3) | 20:31 |
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| hackerfoo | litghost: What consumes synth_tiles_pinmap.csv? | 23:00 |
| litghost | https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc7/make/arch_define.cmake#L45 | 23:00 |
| tpb | Title: symbiflow-arch-defs/arch_define.cmake at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 23:00 |
| mithro | litghost: I needed this patch to make the harnesses build successful.... https://www.irccloud.com/pastebin/0LucohTl/ | 23:34 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 23:34 |
| mithro | litghost: This look good? https://github.com/SymbiFlow/prjxray-db/compare/new-master?expand=1 | 23:49 |
| tpb | Title: Comparing master...new-master · SymbiFlow/prjxray-db · GitHub (at github.com) | 23:49 |
| litghost | Ya | 23:49 |
| mithro | litghost: Still looks like there is some issues with the kintex with missing IOI_LEAF_GCLK0, IOI_IOCLK0 and similar? | 23:53 |
| litghost | mithro: Ya, https://github.com/SymbiFlow/prjxray/pull/1017 is attempting to fix it | 23:53 |
| tpb | Title: Avoid failing on empty pip lists (which may occur). by litghost · Pull Request #1017 · SymbiFlow/prjxray · GitHub (at github.com) | 23:53 |
| litghost | mithro: I think I have the last fix in | 23:53 |
| hzeller[m] | What are the premap..v verilog files generated by yosys used for https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc7/yosys/synth.tcl#L7 ? It does not seem to be needed for the remaining vpr process (I comment them out in symbiflow-simple-sample). I suspect this is just used as a debugging output but it is not something needed in a typical workflow ? Or, in other words: can I assume that input verilog | 23:57 |
| hzeller[m] | output eblif is what typically is needed in a workflow invoking yosys ? | 23:57 |
| tpb | Title: symbiflow-arch-defs/synth.tcl at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 23:57 |
| litghost | hzeller: The premap files can be used to feed Vivado after unmapping some VPR specific flows | 23:58 |
| litghost | hzeller: This allows some A/B comparisions between VPR and Vivado post-synth | 23:58 |
| litghost | hzeller: Going from the fully mapped output is non-trival, so we write out the verilog premapping | 23:59 |
| hzeller[m] | ah ok, but for just using the FOSS toolchain it is not needed | 23:59 |
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