| *** tpb has joined #symbiflow | 00:00 | |
| *** acomodi has quit IRC | 01:29 | |
| *** Bertl is now known as Bertl_zZ | 03:44 | |
| *** citypw has joined #symbiflow | 03:45 | |
| *** Vonter has quit IRC | 03:58 | |
| *** _whitelogger has quit IRC | 04:02 | |
| *** _whitelogger has joined #symbiflow | 04:05 | |
| *** Vonter has joined #symbiflow | 04:07 | |
| *** adjtm_ has joined #symbiflow | 05:33 | |
| *** duck25 has joined #symbiflow | 05:34 | |
| *** anuejn has joined #symbiflow | 05:35 | |
| *** adjtm has quit IRC | 05:36 | |
| *** duck2 has quit IRC | 05:36 | |
| *** anuejn_ has quit IRC | 05:36 | |
| *** proteusguy has quit IRC | 06:05 | |
| *** noahh has quit IRC | 06:13 | |
| *** duck25 is now known as duck2 | 06:15 | |
| *** citypw has quit IRC | 06:31 | |
| *** Vonter has quit IRC | 06:45 | |
| *** Vonter has joined #symbiflow | 06:45 | |
| *** proteusguy has joined #symbiflow | 06:49 | |
| *** citypw has joined #symbiflow | 07:57 | |
| *** OmniMancer has joined #symbiflow | 08:19 | |
| *** citypw has quit IRC | 11:30 | |
| *** acomodi has joined #symbiflow | 11:34 | |
| *** Bertl_zZ is now known as Bertl | 12:36 | |
| *** bjorkintosh has quit IRC | 13:05 | |
| *** bjorkintosh has joined #symbiflow | 13:05 | |
| *** bjorkintosh has quit IRC | 13:43 | |
| *** bjorkintosh has joined #symbiflow | 13:46 | |
| *** Vonter has quit IRC | 13:47 | |
| *** Vonter has joined #symbiflow | 13:49 | |
| *** alexhw has quit IRC | 14:11 | |
| *** bjorkintosh has quit IRC | 14:12 | |
| *** bjorkintosh has joined #symbiflow | 14:23 | |
| *** bjorkintosh has quit IRC | 14:33 | |
| sf-slack2 | <mkurc> @litghost Does it make sense to start working on clock tree synthesis by removing BUFGCTRL and BUFHCE stuff from the harness and adding it to VPR? The harness could provide the input clock wire for example at a HCLK_VBRK tile. That would allow to work on clock routing independently from the IOB stuff. | 14:34 |
|---|---|---|
| sf-slack2 | <butta> We just pulled the newest version of symbiflow-arch-defs and now when running yosys on our tests we get the following error: | 15:15 |
| sf-slack2 | <butta> We just pulled the newest version of symbiflow-arch-defs and now when running yosys on our tests we get the following error: symbiflow-arch-defs/xc7/techmap/cells_map.v:1397: ERROR: Can't resolve task name `\$error'. It looks like the error reporting system $error is undefined. Also, we are getting an error here in the first place which we weren't before and could use help tracking down this error. It's probably | 15:20 |
| sf-slack2 | important to mention that we overwrote brams.txt which confuses things a bit more. | 15:20 |
| *** proteusguy has quit IRC | 15:21 | |
| litghost | Butta: that is a regression in yosys that was fixed yesterday | 15:35 |
| *** citypw has joined #symbiflow | 16:03 | |
| sf-slack2 | <butta> @litghost Alright thanks, we fixed the issue | 16:30 |
| *** proteusguy has joined #symbiflow | 17:09 | |
| *** OmniMancer has quit IRC | 17:17 | |
| *** noahh has joined #symbiflow | 19:13 | |
| litghost | mkurc: I believe we should hold off for now. I think there is plenty of fuzzer work that is required in parallel for https://github.com/SymbiFlow/prjxray/issues/867 , and I think that is the better short term priority. We can re-evaluate depending on how long the IBUF/OBUF effort takes | 19:29 |
| tpb | Title: Create a test design using LiteX, LiteEth and LiteDRAM and figure out what bits are still needed · Issue #867 · SymbiFlow/prjxray · GitHub (at github.com) | 19:29 |
| *** citypw has quit IRC | 19:38 | |
| *** noahh has quit IRC | 21:36 | |
| hackerfoo | RapidWright has some nice documentation of Xilinx terminology: https://www.rapidwright.io/docs/Xilinx_Architecture.html | 22:08 |
| tpb | Title: Xilinx Architecture Terminology RapidWright 2018.3.3-beta documentation (at www.rapidwright.io) | 22:08 |
| *** hackkitten has quit IRC | 22:10 | |
| *** hackkitten has joined #symbiflow | 22:10 | |
| hackerfoo | From https://www.rapidwright.io/docs/Design_Checkpoints.html: A design checkpoint file (extention .dcp) is a Vivado file format that contains a synthesized netlist, design constraints and can contain placement and routing information. RapidWright provides readers and writers to parse and export the various components. | 23:12 |
| sf-slack2 | <pgielda> Its a zip as far as I remember | 23:13 |
| hackerfoo | It should be possible to use their APL2.0 source to generate DCPs. | 23:13 |
| sf-slack2 | <pgielda> (Renamed .zip file) | 23:13 |
| sf-slack2 | <pgielda> (I might be mistaken of course, somebody would have to check) | 23:14 |
| hackerfoo | That's what I figured, but generating/parsing whatever is in the zip isn't always trivial. | 23:14 |
| hackerfoo | The zip has: dcp.xml, top.wdf, top.edf, top_stub.v, top_late.xdc, top_iPhysOpt.tcl, top.xdef, top.rda, top.shape, top.incr, top.xn, top_stub.vhdl | 23:20 |
| hackerfoo | Nevermind. The code to read/write DCPs is under a different license. | 23:26 |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!