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| duck2 | latest symbiflow-arch-defs and conda vpr prints ~140K warnings to the output while building buttons_basys3_bin. am i doing something wrong? | 00:10 |
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| mithro | duck2: You are right about the output be hilarious! http://dpaste.com/2AF5DWF.txt | 06:10 |
| mithro | duck2: No, you should log a bug about that | 06:11 |
| mithro | duck2: (Regarding the vtr errors) | 06:15 |
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| sf-slack2 | <acomodi> duck2, mithro: There is an open PR I am dealing with to make the error/warnings optional: https://github.com/SymbiFlow/vtr-verilog-to-routing/pull/66 | 08:08 |
| tpb | Title: [WIP] vpr: added optional vpr_throw to demote errors to warnings by acomodi · Pull Request #66 · SymbiFlow/vtr-verilog-to-routing · GitHub (at github.com) | 08:08 |
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| sf-slack2 | <mkurc> @mithro I checked Verilator for attribute support and it seems that all cases relevant to us (parameters and port connections) are supported. | 15:17 |
| sf-slack2 | <mkurc> @mithro There is still no feedback on my PR to the Icarus Verilog. | 15:19 |
| sf-slack2 | <mkurc> @mithro Have you consulted with Yosys devs the idea of having wires that mock parameters? (for having attributes on them and preserving default assigned value) Are they willing to accept such a solution? | 15:26 |
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| mithro | mkurc: Do you want to chat with Eddie directly? | 16:34 |
| sf-slack2 | <mkurc> @mithro It makes sense. But unfortunately I don't have time for it today. | 18:00 |
| mithro | mkruc: I sent an introduction | 18:04 |
| sf-slack2 | <mkurc> @mitho: Saw it. Thanks. | 18:06 |
| hackerfoo | It looks like no IOI bits need to set to pass the signal through. I built "buttons" with Vivado, then converted to FASM, and then back to bitstream without the ROI bitstream, and it works. There are no IOI features in the FASM, just IOB. So I can ignore the IO logic for now. | 22:50 |
| litghost | hackerfoo: Yes | 22:52 |
| litghost | hackerfoo: Make sure when you do those kind of experiments you run bit2fasm with "--verbose" to ensure unknown bits are reported | 22:53 |
| litghost | hackerfoo: There should be 0 of them, but best to check | 22:53 |
| hackerfoo | litghost: I did, and there were no unknown bits. | 22:54 |
| litghost | hackerfoo: There is one IOI bit you do need: https://github.com/SymbiFlow/prjxray-db/blob/master/artix7/harness/basys3/swbut/design.json#L3659 | 22:54 |
| tpb | Title: prjxray-db/design.json at master · SymbiFlow/prjxray-db · GitHub (at github.com) | 22:54 |
| litghost | ZINV_D | 22:54 |
| litghost | hackerfoo: Otherwise ILOGIC will invert the signal | 22:55 |
| litghost | hackerfoo: It is worth noting that there is no way to actually invert IBUF signals without the use of an IDDR, which is not going to be the baseline ROI breakout | 22:57 |
| hackerfoo | Why is it IOB_* instead of IOI_*? | 22:59 |
| litghost | hackerfoo: Frankly there is not a strong way to seperate the too from a bitstream perspective, so the initial IOB/IOI fuzzers emit a mix of both | 23:01 |
| litghost | hackerfoo: I don't know if tilegrid even has an entry for IOI tiles yet, as they overlap strongly with the IOB bits | 23:02 |
| litghost | Example: | 23:03 |
| litghost | IOI -> RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.2 30_127 | 23:03 |
| litghost | IOB -> RIOB33.IOB_Y0.INOUT 30_67 | 23:03 |
| litghost | hackerfoo: So we can restructure the fuzzers and tilegrid, but the bits are strongly interwoven | 23:03 |
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