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| hackerfoo | I suppose I should try bit2v in Vivado | 00:01 |
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| litghost | hackerfoo: Is this BRAM or LUT-RAM? | 00:23 |
| litghost | hackerfoo: LUT-RAM I expect to work in autosim | 00:23 |
| litghost | hackerfoo: BRAM lacks sim models stil | 00:23 |
| litghost | l | 00:23 |
| hackerfoo | I think it was both. I'll check in a minute. | 00:23 |
| hackerfoo | I just tried dram_test_64x1d: | 00:29 |
| * hackerfoo posted a file: Screenshot from 2019-05-23 17-20-31.png (197KB) < http://sandbox.hackerfoo.com:8008/_matrix/media/v1/download/sandbox.hackerfoo.com/AVJMXPFAoawgPucVsZuKqZim > | 00:29 | |
| litghost | hackerfoo: The 'x' on the write_enable indicates a problem somewhere | 00:31 |
| hackerfoo | It's probably because rx=x | 00:36 |
| hackerfoo | Nevermind, that only affects the LEDs. | 00:38 |
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| * hackerfoo uploaded an image: Screenshot from 2019-05-23 17-53-44.png (76KB) < http://sandbox.hackerfoo.com:8008/_matrix/media/v1/download/sandbox.hackerfoo.com/RKzCgrGQnPXOMwaRGVyGmSkQ > | 01:03 | |
| hackerfoo | I don't understand why nrst doesn't affect anything. I don't trust the simulation. | 01:03 |
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| sf-slack2 | <acomodi> litghost, mithro: https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/599 this is the zero-capacity PR upstream | 10:08 |
| tpb | Title: check_rr_graph: make zero capacity nodes valid and not drawn. by acomodi · Pull Request #599 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 10:08 |
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| sf-slack2 | <acomodi> litghost, mithro: if all the small patches get merged upstream the only issue preventing upstream VTR to be used in SymbiFlow is the `adjacency check` which now is treated as an error | 13:22 |
| sf-slack2 | <acomodi> litghost, mithro: can you provide some insights on the small PRs I have opened on VTR upstream? https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/599 and https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/600 | 14:04 |
| tpb | Title: check_rr_graph: make zero capacity nodes valid and not drawn. by acomodi · Pull Request #599 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 14:04 |
| sf-slack2 | <tmichalak> @mithro: @litghost: I think we are really close to having a stable prjxray database generation. Apart from dedicated PRs with the remaining fixes I also created a DNM PR with all of them to see if something else comes up before all other PRs get merged. After the merges the only thing left to do is re-enabling the harness generation which was disabled as it would fail due to missing bit definitions. The restored | 14:10 |
| sf-slack2 | harness for Artix should just work. For Zynq however, there is a small change required in the create_design_json script due to some extra bits I am writing about here: https://github.com/SymbiFlow/prjxray/issues/746#issuecomment-490499100 I added a PR (https://github.com/SymbiFlow/prjxray/pull/851) which basically adds a white listing mechanism per architecture in order to successfully pass the generation of design.json | 14:10 |
| sf-slack2 | despite the fact that the white listed bits are not in the database. I tested it along with the xc7frames2bit PR in symbiflow-arch-defs and the counter example on the Zybo board worked. | 14:10 |
| tpb | Title: unknown bit in zynq7 harness · Issue #746 · SymbiFlow/prjxray · GitHub (at github.com) | 14:10 |
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| sf-slack2 | <acomodi> mode selection feature merged! :slightly_smiling_face: | 16:14 |
| litghost | acomodi: Yay! | 16:16 |
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