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sf-slack2 | <acomodi> mithro: now https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/518 is complete | 13:48 |
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tpb | Title: Eblif write support by acomodi · Pull Request #518 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 13:48 |
sf-slack2 | <acomodi> mithro: it correctly writes both .params and .attrs in the output blif | 13:48 |
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mithro | kgugala: Your idea of using yosys on the .sim.v files is a pretty good idea | 15:51 |
sf-slack2 | <kgugala> @mithro I did some initial tests on that and implemented a simple python tool for updating blif generated from those sim.v files so they correspond with what the test architecture expects | 15:54 |
mithro | kgugala: https://github.com/SymbiFlow/symbiflow-arch-defs/issues/746 | 15:56 |
tpb | Title: Use Yosys on .sim.v files to generate a .eblif needed for architecture testing · Issue #746 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 15:56 |
sf-slack2 | <kgugala> @mithro we have a WIP implementation of points 1 to 3 of the above issue | 15:58 |
sf-slack2 | <kgugala> I'll open a PR later | 15:58 |
mithro | kgugala: Great! | 15:59 |
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mithro | mkurc: https://github.com/SymbiFlow/symbiflow-arch-defs/issues/748 | 16:37 |
tpb | Title: Add v2x to use specify section rather than the extra timing attributes · Issue #748 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 16:37 |
mithro | mkurc: https://github.com/SymbiFlow/symbiflow-arch-defs/issues/749 | 16:41 |
tpb | Title: Add support for loading timing information in v2x from SDF · Issue #749 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 16:41 |
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mithro | mkurc / kgugala: https://github.com/SymbiFlow/symbiflow-arch-defs/pull/681 | 16:59 |
tpb | Title: WIP - Tool for generating stuff related to latches by mithro · Pull Request #681 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 16:59 |
mithro | mkurc / kgugala: https://docs.google.com/spreadsheets/d/16yvScRkedOkPCRBSInFuHE_cUMD8Ls-b9KFmHocpC-o/edit#gid=0 | 17:01 |
tpb | Title: Flip Flops - Google Sheets (at docs.google.com) | 17:01 |
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hackerfoo | Apparently Vivado infers the NO_CHANGE write mode for block RAM even if you specify READ_FIRST. | 21:05 |
litghost | hackerfoo: There are cases where NO_CHANGE is equiv, but presumably that is an optimization? | 21:06 |
litghost | hackerfoo: Read the memory guide, I believe there is a paragraph describing this behavior? | 21:07 |
hackerfoo | Yeah, I know, I just didn't expect it to do that for me. | 21:07 |
hackerfoo | Probably only when you have a single write port, which is a pretty simple test. | 21:08 |
litghost | hackerfoo: If I had to guess, maybe Vivado proved that write and reading over the same address was impossible, so NO_CHANGE is equiv to READ_FIRST? | 21:08 |
hackerfoo | Okay - It's also ignoring WRITE_FIRST? That doesn't seem right. | 21:10 |
litghost | hackerfoo: If there is never a read/write address conflict, the write mode doesn't matter | 21:10 |
litghost | hackerfoo: And NO_CHANGE is the least power/fastest mode | 21:11 |
litghost | hackerfoo: WRITE_FIRST/READ_FIRST/NO_CHANGE have an impact if a read and write of the same address occurs in one cycle | 21:11 |
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hackerfoo | litghost: Ah, DO of the write port isn't connected so it really doesn't matter. | 22:36 |
litghost | hackerfoo: Right, so the mode is unobservable, in which case the cheapest/fastest mode should be used | 22:40 |
litghost | hackerfoo: FYI this simple optimization (DO/DOP disconnected -> NO_CHANGE) is fairly easy to write in the techmap | 22:41 |
litghost | hackerfoo: We don't have to do it at the first cut, but it isn't hard to do | 22:41 |
hackerfoo | I think I'm just going to keep it simple for now, and just do widths of 8/9, 16/18, and 32/36 for now, and no optimizations. | 22:44 |
litghost | hackerfoo: I agree | 22:46 |
litghost | hackerfoo: It seems reasonable to write a short issue with the known limitations of the current approach and what work could be done to make it complete | 22:47 |
hackerfoo | Yeah | 22:47 |
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