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| sf-slack2 | <acomodi> By checking the placement costs it is noticeable that with equivalent tiles we get a lower cost with placement. Here some data: https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/559#issuecomment-493398524 | 10:14 |
|---|---|---|
| tpb | Title: WIP: Equivalent Tiles placement by acomodi · Pull Request #559 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 10:14 |
| sf-slack2 | <acomodi> I wonder what will be the reduction when timing is added as well. | 10:14 |
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| litghost | acomodi: Interesting! Hopefully I'll be able to add some numbers once I get the timing stuff closing | 15:11 |
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| litghost | https://github.com/SymbiFlow/symbiflow-arch-defs/issues/716#issuecomment-493499359 VPR can now correctly know that it produced a design that fails timing (yay!) | 15:50 |
| tpb | Title: [XC7] Timing quality tracking bug · Issue #716 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 15:50 |
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| sf-slack2 | <acomodi> litghost: Great! does VPR know that the clock frequency is 100MHz (for basys3)? | 15:56 |
| litghost | acomodi: That simply comes from the SDF (which I've hard wired for now) | 15:57 |
| litghost | http://docs.verilogtorouting.org/en/latest/vpr/sdc_commands/#create-clock | 15:57 |
| tpb | Title: SDC Commands Verilog-to-Routing 8.0.0-dev documentation (at docs.verilogtorouting.org) | 15:57 |
| litghost | SDC sorry not SDF | 15:57 |
| sf-slack2 | <acomodi> litghost: Ok, good to know. So the issue now is that VPR is not able to find a routing with a critical path of less than 10ns, right? | 16:00 |
| sf-slack2 | <acomodi> litghost: Or it doesn't even try again after failing? | 16:01 |
| litghost | acomodi: Unclear, likely this particular issue is a side affect of aggressive packing | 16:02 |
| litghost | acomodi: My next step is to make sure that VPR is chasing the actual critical path | 16:03 |
| sf-slack2 | <acomodi> litghost: Got it, so you could understand if it is actually trying to solve it. Have you tried to use timing based routing and placement on designs (murax or scalable-proc) we are sure are working on HW? | 16:06 |
| litghost | acomodi: Ya, this is with timing based placement and routing | 16:07 |
| litghost | acomodi: FYI, just because something works on hardware does not mean it meets timing. The timing analysis is examining worst case setup conditions (and hold), and on our test setups we are likely not running at the SLOW corner | 16:09 |
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| elms | "Simulating an FPGA with an FPGA" https://blog.hackster.io/our-5-favorite-cornell-university-student-fpga-projects-683cffcda0d2#6cff | 18:40 |
| tpb | Title: Our 5 Favorite Cornell University Student FPGA Projects (at blog.hackster.io) | 18:40 |
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| mithro | These students have taken that concept into an existential direction by using an Intel Cyclone5 FPGA to simulate an Xilinx XC6200 FPGA. | 21:11 |
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