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| hackerfoo | No, I guess not, because all these pins still need to be routed. | 00:01 |
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| litghost | hackerfoo: Ya, tying of nets should be done in techmap | 00:44 |
| litghost | hackerfoo: Word of warning on fasm2v, it currently lacks the logic to handle disambiguiating 2 RAM18E1's versus 1 RAM36E1 | 00:45 |
| litghost | hackerfoo: There is support for adding such cleanup, but because VPR didn't have RAM36E1 support, I didn't implement that cleanup step | 00:46 |
| litghost | hackerfoo: As far as I can tell the only difference from a FASM standpoint between RAM18E1 and RAM36E1 is how those upper address lines are routed | 00:46 |
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| litghost | hackerfoo: If the high address lines are tied high, than it is two independent RAM18E1, if tied to signals one RAM36E1 | 00:47 |
| litghost | hackerfoo: I don't have a good mental model of how this all works out | 00:47 |
| hackerfoo | That's similar to how tying A6 high keeps O5/O6 independent for two DPRAM32s. | 00:49 |
| hackerfoo | Once I get the 36k block working, I'll try drawing some schematics. | 00:50 |
| litghost | hackerfoo: If the scheme is the same as DPRAMs, that implies interesting things about the data ports which I don't think is supported by the routing. It'll be interesting to see the schematics | 00:52 |
| litghost | hackerfoo: Read data ports specifically | 00:52 |
| hackerfoo | Any idea why is RSTRAMARSTRAML called RSTRAMARSTRAMLRST in the db? It's RSTRAMARSTRAML in Vivado as expected. | 01:19 |
| litghost | Link? | 01:19 |
| hackerfoo | https://github.com/SymbiFlow/symbiflow-arch-defs/blob/dba00415ae607c6b5768c4c3c0d2626839ecc702/xc7/primitives/bram/bram.pb_type.xml#L39 | 01:21 |
| tpb | Title: symbiflow-arch-defs/bram.pb_type.xml at dba00415ae607c6b5768c4c3c0d2626839ecc702 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 01:21 |
| litghost | That should match a wire name | 01:21 |
| litghost | Check the name of the wire, rather than the port name | 01:21 |
| litghost | Could just be a typo! | 01:22 |
| litghost | I just checked, and the wire does not have that last RST | 01:23 |
| hackerfoo | How do I fix it? | 01:24 |
| litghost | Presumably that wire was never getting connected at the top level pb, so just rename the port :) | 01:25 |
| litghost | Interesting, I just check the generated top level pb, and it does have the post-fix | 01:26 |
| litghost | :/ | 01:26 |
| litghost | Ah, I was look at the wrong wire | 01:27 |
| litghost | You might have been too | 01:27 |
| hackerfoo | I guess I'll just do a global search-and-replace, but it's probably somewhere in prjxray that generates the db. | 01:27 |
| litghost | RSTRAMARSTRAMLRST != RSTREGARSTREGL | 01:27 |
| litghost | RSTRAMARSTRAMLRST is the correct wire name | 01:27 |
| litghost | The current port name is correct | 01:27 |
| litghost | To show it in vivado run: | 01:28 |
| litghost | select_objects [get_nodes BRAM_L_X6Y135/BRAM_FIFO36_RSTRAMARSTRAMLRST] | 01:28 |
| litghost | So sorry for the confusion, but the port is actually named correctly | 01:29 |
| hackerfoo | Then where is RSTRAMARSTRAML? | 01:29 |
| * hackerfoo uploaded an image: Screenshot from 2019-05-14 18-16-06.png (8KB) < http://sandbox.hackerfoo.com:8008/_matrix/media/v1/download/sandbox.hackerfoo.com/KdHMKXNBcWXHvDxBdPFovxAN > | 01:30 | |
| hackerfoo | Right under RSTRAMARSTRAMU | 01:30 |
| hackerfoo | This is my design just using Vivado. | 01:31 |
| hackerfoo | Also, it follows the U/L naming scheme for inputs into the two halves of the RAMB36E1. | 01:33 |
| hackerfoo | I'm pretty sure it's a typo. | 01:33 |
| hackerfoo | I blame Xilinx for their ridiculous names. | 01:36 |
| litghost | hackerfoo: Oh, you are looking at the block in RAM36E1 mode | 01:36 |
| litghost | hackerfoo: Click the wire itself, and it will have the RST postfix | 01:37 |
| litghost | hackerfoo: And if you check a block in "RAMBFIFO36E1 (primary)" you'll see the port name change | 01:37 |
| litghost | hackerfoo: Super fun | 01:37 |
| hackerfoo | Can you send a screenshot? I only have GLOBAL_LOGIC1 | 01:38 |
| * hackerfoo uploaded an image: Screenshot from 2019-05-14 18-32-55.png (6KB) < http://sandbox.hackerfoo.com:8008/_matrix/media/v1/download/sandbox.hackerfoo.com/mXVWFGnvozPKDaxDFvKGAdxG > | 01:41 | |
| mithro | duck2's first contribution as part of GSoC! https://github.com/SymbiFlow/vtr-verilog-to-routing/pull/51 | 01:43 |
| tpb | Title: Enable PugiXML compact mode by duck2 · Pull Request #51 · SymbiFlow/vtr-verilog-to-routing · GitHub (at github.com) | 01:43 |
| duck2 | yay :P the sax reader was much bigger, but the fastest sax parser is 3x slower than pugixml, so it kind of failed. | 01:47 |
| litghost | hackerfoo: You are selecting the net, not the wire or node | 02:21 |
| litghost | hackerfoo: Click again and it will select the node and then the wire | 02:21 |
| hackerfoo | Okay, I'm pretty sure that's a typo on Vivado's end: | 03:02 |
| * hackerfoo uploaded an image: Screenshot from 2019-05-14 19-51-49.png (16KB) < http://sandbox.hackerfoo.com:8008/_matrix/media/v1/download/sandbox.hackerfoo.com/PavprCKUBzETmGxgiIrELcOK > | 03:02 | |
| * hackerfoo uploaded an image: Screenshot from 2019-05-14 19-53-32.png (15KB) < http://sandbox.hackerfoo.com:8008/_matrix/media/v1/download/sandbox.hackerfoo.com/BPnLjKGHOoBhHpIhVbXHpAci > | 03:02 | |
| hackerfoo | litghost: Should we copy Vivado's typos? | 03:03 |
| litghost | hackerfoo: Yes | 03:03 |
| litghost | hackerfoo: Because it isn't a typo | 03:04 |
| hackerfoo | Why? What does it mean? | 03:04 |
| litghost | hackerfoo: The way to read it is "RSTRAMA | RSTRAML | RST" | 03:04 |
| hackerfoo | The U pin doesn't have the RST suffix. | 03:04 |
| litghost | hackerfoo: Flip through the 3 modes of the RAMB36E1 and you will see why | 03:05 |
| litghost | hackerfoo: Actually the way to read it is "RSTRAMARSTRAML (RAMB36E1) | RST (FIFO36E1)" | 03:06 |
| hackerfoo | Ah. Why can't they use an underscore or something? | 03:07 |
| hackerfoo | litghost: Is there an easy way to flip through the modes? | 03:16 |
| litghost | hackerfoo: Just select an unselected BRAM36E1 cell, and then select the type in site properties window | 03:17 |
| hackerfoo | litghost: Thanks | 03:34 |
| hackerfoo | https://www.microsoft.com/en-us/research/publication/the-feniks-fpga-operating-system-for-cloud-computing/ | 03:48 |
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| sf-slack2 | <acomodi> litghost: I would need some feedback on my comment of this issue: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/513#issuecomment-492225837. Does it sound correct? | 14:49 |
| tpb | Title: Support Equivalent Placement Sites · Issue #513 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 14:49 |
| sf-slack2 | <acomodi> litghost: mainly because I believe that the change described in the comment requires a moderate amount of effort | 14:51 |
| litghost | acomodi: Sorry, can you provide more context? | 15:03 |
| litghost | acomodi: I haven't seen a comment from the VTR dev's since 27 days ago | 15:03 |
| litghost | acomodi: Why not have them first look at the implementation you have done, and evaluate it | 15:04 |
| litghost | acomodi: Rather than preemptively conforming to another design | 15:04 |
| sf-slack2 | <acomodi> litghost: Ok, makes sense, I wanted to explore other possible designs and see if they were implementable. | 15:10 |
| sf-slack2 | <acomodi> litghost: in the meanwhile though I am stalled until there is a preliminary evaluation. What do you think could I focus on? | 15:11 |
| litghost | acomodi: If you think the suggestion in the issue is worth pursuing I won't stop you, but my understanding is we have an implementation that works. How do the performance before/after numbers look? | 15:16 |
| litghost | acomodi: I would suggest ROI breakout work, e.g. VPR tiles for the clock column and IOB's | 15:20 |
| sf-slack2 | <acomodi> litghost: ok first I will get some reports (e.g. run_time and placement cost), but I can extract those only from Symbiflow xc7 tests as equivalent tiles is supported only by those right now | 15:21 |
| litghost | acomodi: Oh, you need to write the arch top-level pb_type to tiles tool | 15:21 |
| litghost | acomodi: Did that happen? | 15:21 |
| litghost | acomodi: Because you should be able to run against the full suite through the tool, yes? | 15:22 |
| sf-slack2 | <acomodi> litghost: you mean VTR test suite or the symbiflow one? | 15:23 |
| litghost | acomodi: VTR test suite | 15:26 |
| sf-slack2 | <acomodi> litghost: anyway there is an initial PR with a script that moves the top level pb_types to the tiles tag (without adding the equivalent tiles though) https://github.com/SymbiFlow/symbiflow-arch-defs/pull/583 | 15:27 |
| tpb | Title: WIP: added script to add tiles tag and equivalent tiles by acomodi · Pull Request #583 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 15:27 |
| litghost | acomodi: But I believe there was agreement that script needed to live in VPR? | 15:28 |
| litghost | acomodi: Unless your PR allows old style arch-xml's to work as is? | 15:28 |
| litghost | acomodi: I thought your PR required the new style tiles definition? | 15:28 |
| sf-slack2 | <acomodi> litghost: No, the script is needed as the pb_type cannot have some child tags anymore (e.g. fc, pinlocations, ...) | 15:29 |
| litghost | acomodi: I think we agree that the script is needed, and it should be a part of VPR because anyone using VPR would be affected | 15:30 |
| litghost | acomodi: Not just symbiflow | 15:30 |
| sf-slack2 | <acomodi> litghost: Yes indeed, in fact I do believe that it will take a while before the PR will get merged as it introduces a great change in the whole architecture definition | 15:31 |
| sf-slack2 | <acomodi> litghost: I will add the script to VPR then | 15:31 |
| litghost | acomodi: I think discussing that point directly with the VTR devs is worth doing | 15:32 |
| sf-slack2 | <acomodi> litghost: to make CI green on VPR and be able to test on all the architectures | 15:32 |
| litghost | acomodi: Yes | 15:32 |
| litghost | acomodi: There is an open question in my mind if VTR should do the top level pb_type to tile conversion internally to avoid requiring a format change | 15:33 |
| litghost | acomodi: But I'll let the VTR devs drive that choice | 15:33 |
| sf-slack2 | <acomodi> litghost: you mean change all the architectures to be compliant with the new tiles concept instead of using a script at runtime? | 15:35 |
| litghost | acomodi: As a fallback, or something | 15:36 |
| litghost | acomodi: Or maybe a config flag | 15:36 |
| litghost | acomodi: I haven't thought my about this, I'm just trying to explore other avenues to avoid required a lot of action for endusers of VPR | 15:38 |
| litghost | much* | 15:38 |
| litghost | acomodi: Overall, I would let the VRP devs guide the conversion on the breaking of backwards capability | 15:39 |
| sf-slack2 | <acomodi> litghost: Makes sense. In fact, for now it is better to rely on a script, but it surely is something to discuss with VPR devs as you said | 15:43 |
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| mithro | elms: If you are okay with it, O | 16:55 |
| mithro | bah | 16:55 |
| mithro | elms: If you are okay with it, I'll merge https://github.com/SymbiFlow/symbiflow-arch-defs/pull/731 | 16:55 |
| tpb | Title: travis: Enable running scripts locally. by mithro · Pull Request #731 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 16:55 |
| elms | mithro: LGTM | 16:56 |
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| mithro | acomodi: my preference is that we have a script which can do the conversion and only support the new format directly | 20:49 |
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