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| mithro | litghost: We don't have a `add_file_target(FILE "xxx.py" SCANNER_TYPE python)` right? | 00:03 |
|---|---|---|
| litghost | mithro: We do not | 00:03 |
| litghost | mithro: I've thought about it | 00:03 |
| mithro | Should we? | 00:03 |
| litghost | mithro: Frankly, if we go that route, we probably should've just stuck with bazel | 00:03 |
| litghost | mithro: I assume you ran into a case where a target didn't rebuild because of a library? | 00:04 |
| mithro | litghost: No, more I just noticed it was missing when fixing stuff for your comments... | 00:04 |
| litghost | mithro: The primary reason we don't have a python scanner is we don't really build any python files | 00:05 |
| litghost | mithro: Unlike verilog and xml's | 00:05 |
| litghost | mithro: So the dependency tracking is significantly weaker | 00:05 |
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| mithro | kgugala: You might want to look at https://github.com/SymbiFlow/symbiflow-arch-defs/pull/672 | 03:12 |
| tpb | Title: v2x: Run output produced through vpr by mithro · Pull Request #672 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 03:12 |
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| sf-slack2 | <kgugala> @mithro, sure I'm looking into that | 14:29 |
| sf-slack2 | <acomodi> litghost, mithro: I have re-run the test for the mode-selection on the master VTR branch (`strong_routing_mode`) and got the errors described in https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/517#issuecomment-490103974 | 14:39 |
| tpb | Title: Mode selection feature by acomodi · Pull Request #517 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 14:39 |
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| sf-slack2 | <acomodi> litghost, mithro: could you confirm whether the first error is correct? | 14:40 |
| sf-slack2 | <acomodi> *do you | 14:41 |
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| sf-slack2 | <kgugala> @mithro do you want me to take a look on https://github.com/SymbiFlow/symbiflow-arch-defs/pull/672#issuecomment-490116077 ? | 15:05 |
| tpb | Title: v2x: Run output produced through vpr by mithro · Pull Request #672 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 15:05 |
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| mithro | Morning | 15:57 |
| mithro | kgugala: Less for review and more for checking that things you are generating work with it | 15:57 |
| litghost | acomodi: Your errors look good. Should help MohamedEldafrawy look into the issue | 16:00 |
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| sf-slack2 | <acomodi> litghost: ok, I will provide him with all the necessary information | 16:04 |
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| mithro | kgugala: https://docs.google.com/document/d/1bkI14f-nvJnHIDMIdHB_nNTWToCDg8Ys_wARZHRylq4/edit | 16:48 |
| tpb | Title: [Temporary] v2x stuff to merge - Google Docs (at docs.google.com) | 16:48 |
| sf-slack2 | <kgugala> I think @mkurc should also take a look on this doc | 16:52 |
| sf-slack2 | <mkurc> @kgugala Looking... | 16:52 |
| sf-slack2 | <acomodi> litghost: one question, now that the split is on, is the `specialize carrychain` still required? | 16:52 |
| litghost | acomodi: Good question. I don't know | 16:53 |
| litghost | acomodi: I think this is a case where without timing information, it is hard to evaluate the quality of output before and after | 16:54 |
| litghost | acomodi: I recommend we focus on getting equivilant tiles landed, and timing | 16:54 |
| litghost | acomodi: And after that, we can evaluate specialize vs no specialize and round robin vs no round robin | 16:54 |
| litghost | acomodi: I think letting result quality be our guide once we have results will help make descisions | 16:55 |
| sf-slack2 | <acomodi> litghost: Agreed, it just popped up in my mind. For sure it is something that can be postponed | 16:56 |
| litghost | acomodi: Let's make sure an issue is tracking the idea | 16:57 |
| sf-slack2 | <acomodi> litghost: I'm on it | 16:57 |
| litghost | acomodi: Oh, okay | 16:58 |
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| mithro | kgugala / mkurc: For now I think in v2x / sim.v files I think we should use explicit mux specification rather than implicit mux inference | 17:25 |
| sf-slack2 | <kgugala> @mithro I agree | 17:26 |
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| mithro | kgugala / mkurc: I added a quick section at the top on how I think we should handle all the things | 17:51 |
| hackerfoo | I noticed read_uart.py is discarding some data, since it just reads 10KB at a time. Is it worth making read_uart.py and error_output_logic.v more robust? | 17:55 |
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| hackerfoo | (in arch-defs/xc7/tests/common) | 18:07 |
| litghost | hackerfoo: Yes/no. I'd start with just adding the RAM32M test, and then maybe as a follow up improving error_output_logic.v | 18:08 |
| hackerfoo | litghost: Okay, agreed. | 18:09 |
| hackerfoo | Has ERROR_OUTPUT_LOGIC.DATA_WIDTH(2) been tested? I'm getting 'E' right now, but read_uart.py doesn't seem to parse it because it doesn't print anything, it just happily munches all the data. | 18:12 |
| litghost | hackerfoo: No, but I believe DATA_WIDTH(16) is being used with BRAM | 18:12 |
| litghost | and DATA_WIDTH(32) I believe? | 18:12 |
| hackerfoo | Yes, in bram_sdp_test. Hmm. | 18:14 |
| litghost | hackerfoo: I recommend starting with | 18:14 |
| litghost | stty raw 500000 < /dev/ttyUSBX | 18:14 |
| litghost | xxd /dev/ttyUSBX | 18:14 |
| litghost | hackerfoo: Or redirect to a file and use xxd | 18:15 |
| hackerfoo | Yeah, I did that. That works, and I get 'E'', so I didn't want to manually parse the results to debug it. | 18:15 |
| hackerfoo | I'm tempted to make error_output_logic.v dump ASCII hex over the UART. | 18:16 |
| hackerfoo | And end records with \n. | 18:17 |
| hackerfoo | Anyway, I should just fix read_uart.py | 18:18 |
| litghost | hackerfoo: I avoided bin -> ASCII because I wanted to keep resource utilization low | 18:18 |
| litghost | hackerfoo: But because we are fairly stable for the combintorial elements, it's probably safe | 18:19 |
| litghost | hackerfoo: Just make sure the bin -> ASCII is implemented as combintorial elements, and not another LUT-RAM | 18:19 |
| hackerfoo | Okay | 18:20 |
| hackerfoo | Should just be shifting and '0' + data[3:0] | 18:21 |
| hackerfoo | Ah, not for A-F. | 18:22 |
| litghost | hackerfoo: Exactly | 18:22 |
| litghost | hackerfoo: You should output ASCII octal | 18:22 |
| litghost | could* | 18:22 |
| litghost | hackerfoo: FYI 9-scalable proc does bin -> hex | 18:22 |
| hackerfoo | I find hex a lot easier to read. | 18:23 |
| hackerfoo | Hopefully a branch for 0-9 and A-F shouldn't be too bad. | 18:24 |
| hackerfoo | Ah, scalable_proc uses a case statement. I'll have to try that. It probably gets synthesized as a LUT. | 18:28 |
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| sf-slack2 | <acomodi> so, with https://github.com/SymbiFlow/symbiflow-arch-defs/pull/691, xc7 CI takes ~69 minutes, not a great improvement, but it's still something | 20:37 |
| litghost | acomodi: :( | 20:39 |
| litghost | acomodi: That is an improvement of 16 minutes, so it isn't nothing | 20:40 |
| sf-slack2 | <acomodi> litghost: well, if put in percentage it's a ~19% improvement which looks much better. let me rephrase: it is a good improvement :slightly_smiling_face: | 20:56 |
| hackerfoo | Is it bad practice to leave inputs disconnected in Verilog if they don't matter? I know it's not good to let inputs float. | 22:07 |
| hackerfoo | And if so, is it better to set them high than low? | 22:08 |
| litghost | hackerfoo: Disconnected is fine if they are truly don't care | 22:14 |
| litghost | hackerfoo: The hardware will always set them to something stable | 22:14 |
| hackerfoo | Okay, thanks. | 22:14 |
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