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| mithro | Morning! | 14:50 |
|---|---|---|
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| sf-slack2 | <kgugala> Morning | 15:03 |
| sf-slack2 | <pgielda> Afternoon ;) | 15:05 |
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| mithro | kgugla: How goes the bel timing import? | 17:17 |
| sf-slack2 | <kgugala> @mithro: I just pushed common timings merge, so now, the last step - use those in the code I implemented for arch-defs | 17:23 |
| sf-slack2 | <kgugala> the merge is a part of this PR https://github.com/SymbiFlow/prjxray/pull/706 | 17:23 |
| tpb | Title: fuzzers: timings: add bel timing fuzzer by kgugala · Pull Request #706 · SymbiFlow/prjxray · GitHub (at github.com) | 17:23 |
| sf-slack2 | <kgugala> for merging I needed the emit functionality of python-sdf-timing | 17:24 |
| sf-slack2 | <kgugala> which was implemented over the easter weekend (+ fixed a lot of bugs in the sdf-timing lib) | 17:25 |
| kgugala | there is also v2x issue with arrays of modules (listed here https://github.com/SymbiFlow/symbiflow-arch-defs/issues/595) | 17:29 |
| tpb | Title: v2x features to replace XML generation · Issue #595 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 17:29 |
| kgugala | IMO, this would have to be fixed before we can migrate from hand written xmls to the generated from verilog ones | 17:31 |
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| mithro | Looks like clifford is adding specify support to Yosys -> https://github.com/YosysHQ/yosys/pull/946 | 19:12 |
| tpb | Title: Add specify parser by cliffordwolf · Pull Request #946 · YosysHQ/yosys · GitHub (at github.com) | 19:12 |
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| JuanP | Hello, in page https://symbiflow.github.io/prjtrellis-db/ECP5/tilehtml/PLC2.html, I don't get the meaning of E1_H02W0501 and the 1s in the F0B2 and F2B2. Are the latter some descriptive bits? Thanks | 19:29 |
| JuanP | I don't get the bigger picture of this | 19:29 |
| daveshah | E1_H02W0501 -> wire H02W0501 one to the east | 19:42 |
| daveshah | F0B2 -> frame 0 bit 2 | 19:43 |
| daveshah | The 1s in F0B2, etc are the bits set to enable that connection | 19:43 |
| daveshah | I explain a bit here: https://youtu.be/cTOkgDZli_o | 19:43 |
| JuanP | Thanks you Dave. I spent the whole we to review the code of Yosys, NextPNR and trellis. This is the only thing I wasn't really sure about | 19:45 |
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| hackerfoo | Does anyone know why RAM64M is commented out in xc7/techmap/cells_map.v? | 20:18 |
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| mithro | hackerfoo: So I think you want to get the "echo" files produce when running the test | 20:26 |
| hackerfoo | For which test? I don't see any for RAM64M. | 20:29 |
| hackerfoo | mithro: ^ | 20:29 |
| mithro | hackerfoo: It is a bit confusing to me why the DRAM128_DP pack-pattern is on both the DPO and SPO direct thingies... | 20:29 |
| mithro | There should be a prepack file which has the molecules in it... | 20:33 |
| hackerfoo | Thanks, I found it. | 20:35 |
| mithro | hackerfoo: There is an interesting comment at the top of dpram128.pb_type.xml -> https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc7/primitives/slicem/Ndram/dpram128.pb_type.xml#L1-L7 | 20:35 |
| tpb | Title: symbiflow-arch-defs/dpram128.pb_type.xml at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 20:35 |
| mithro | hackerfoo: It also looks like some of those comments might be wrong.... | 20:36 |
| hackerfoo | Yeah... | 20:36 |
| mithro | hackerfoo: I think that pack-pattern is suppose to join two 128 bit LUT rams together into a molecule so that WAUSED is correctly set... | 20:41 |
| mithro | hackerfoo: The other pack patterns in this file seem to be called DRAM128 and DRAM128_D... | 20:43 |
| hackerfoo | I don't see DPRAM128 in the diagram for RAM128X1D, or anywhere else in the CLB user guide. Aren't we using the same names as in the guide? | 20:43 |
| mithro | hackerfoo: This CL might help.... https://github.com/SymbiFlow/symbiflow-arch-defs/commit/e5a282fa7f6003dd826a6501f09be50708cff395 | 20:46 |
| tpb | Title: Add stubs for RAMs. · SymbiFlow/symbiflow-arch-defs@e5a282f · GitHub (at github.com) | 20:46 |
| hackerfoo | mithro: here? https://github.com/SymbiFlow/symbiflow-arch-defs/commit/e5a282fa7f6003dd826a6501f09be50708cff395#diff-8340ba8a38e12a98b55999746e9c2eaaR575 | 20:55 |
| tpb | Title: Add stubs for RAMs. · SymbiFlow/symbiflow-arch-defs@e5a282f · GitHub (at github.com) | 20:55 |
| hackerfoo | I think I need to read more before I can make sense out of this. | 20:55 |
| hackerfoo | I'm looking at slicem.pb_type.xml, but I can't see what's out of place yet. | 20:56 |
| mithro | hackerfoo: What does the molecule echo file show? | 20:57 |
| hackerfoo | https://gist.github.com/HackerFoo/606cbb5250263b201d6b0f7c7714d0b7 | 20:59 |
| tpb | Title: pre_packing_molecules_and_patterns.echo · GitHub (at gist.github.com) | 20:59 |
| mithro | hackerfoo: The important one is that last molecule; | 21:02 |
| mithro | https://www.irccloud.com/pastebin/8V4cHWeD/ | 21:02 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 21:02 |
| mithro | hackerfoo: pack-patterns have two usages -- they are either for | 21:03 |
| mithro | (a) carry chains | 21:03 |
| hackerfoo | Okay, I'm not sure what ram0.stub is, but that seems problematic? | 21:03 |
| mithro | (b) Combining small parts into large parts which should be grouped together | 21:03 |
| mithro | There is some info about it here -> https://vtr-verilog-to-routing.readthedocs.io/en/latest/arch/reference.html#tag-interconnect-pack_pattern | 21:04 |
| tpb | Title: Architecture Reference Verilog-to-Routing 8.0.0-dev documentation (at vtr-verilog-to-routing.readthedocs.io) | 21:04 |
| hackerfoo | Thanks | 21:04 |
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| mithro | hackerfoo: It is unclear to me why a pack-pattern of f7a_mux stub f7b_mux makes sense... | 21:10 |
| mithro | hackerfoo: it is also unclear to me why someone would name something just "stub" | 21:11 |
| hackerfoo | mithro: Yeah. I'll look into that and see where it's coming from. | 21:11 |
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| hackerfoo | It looks like those lines in the commit, but I'm not sure what it should be. I'll try reverting them and see what I get. | 21:17 |
| hackerfoo | The stub is to group the DRAMs: "To ensure that all DRAMs are co-located within a SLICE, this block is a simple passthrough black box to allow a pack pattern for dual port DRAMs." | 21:26 |
| hackerfoo | But I'm not sure where ram0.stub is coming from. Maybe it gets eliminated later? It's just 2 wires of output = input. | 21:28 |
| mithro | https://github.com/YosysHQ/yosys/blob/xc7mux/techlibs/xilinx/abc.box | 21:46 |
| tpb | Title: yosys/abc.box at xc7mux · YosysHQ/yosys · GitHub (at github.com) | 21:47 |
| mithro | https://github.com/YosysHQ/yosys/blob/xc7mux/techlibs/xilinx/abc.lut | 21:47 |
| tpb | Title: yosys/abc.lut at xc7mux · YosysHQ/yosys · GitHub (at github.com) | 21:47 |
| hackerfoo | https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc7/techmap/cells_map.v#L386-L388 <- stub | 21:50 |
| tpb | Title: symbiflow-arch-defs/cells_map.v at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 21:50 |
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| mithro | elms: https://docs.google.com/document/d/1waqO7CYT5d9sbTKBU1-2GvFIlgRRWsusPZTYY2EfC4c/edit# | 22:19 |
| tpb | Title: FASM on iCE40 - Google Docs (at docs.google.com) | 22:19 |
| mithro | elms: https://docs.google.com/document/d/1Zt8Jve7EA0Ieck8tAZxawcQm32Cu9oT6vQHaqaaFdOQ/edit# | 22:19 |
| tpb | Title: SymbiFlow iCE40 Verilog to Routing Status - Google Docs (at docs.google.com) | 22:19 |
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| mithro | hackerfoo1: I logged https://github.com/SymbiFlow/symbiflow-arch-defs/issues/616 earlier | 23:48 |
| tpb | Title: Rename distributed ram (DRAM) to LUT ram · Issue #616 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 23:48 |
| mithro | hackerfoo1: Are you going to log an issue about the naming and stuff? | 23:51 |
| hackerfoo1 | Yes, I am. | 23:51 |
| mithro | okay great | 23:51 |
| mithro | Will add my 2 cents after you finish | 23:51 |
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