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| sf-slack | <mgielda> @duck2 @risto.pejasinovic - what's the status of the GSoC applications? | 09:43 |
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| ayumis13 | hello everyone, I am writing the proposal for the GSOC 19 for the project python library for generating VTR arch.xml files . Just wanted to ask if this project is the part of the program. | 10:21 |
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| sf-slack | <mgielda> is this an issue from the ideas list | 10:51 |
| sf-slack | <mgielda> ? | 10:51 |
| sf-slack | <risto.pejasinovic> @mgielda I think I took too much to write quality proposal, for the little time I had. I have the general idea but not enough details. I uploaded draft, I am open to opinions. | 10:55 |
| sf-slack | <mgielda> can you link to the draft? | 10:56 |
| sf-slack | <mgielda> (hard to give opinions without seeing it) | 10:56 |
| sf-slack | <risto.pejasinovic> https://docs.google.com/document/d/11ub2RSJ02Aenqj1DmMTb994sVdaB6PFgpNI-BK3PWXE/edit | 10:56 |
| tpb | Title: Draft proposal for SymbiFlow GSoC - Google Docs (at docs.google.com) | 10:56 |
| sf-slack | <risto.pejasinovic> Sorry I think you can see it from GSoC | 10:56 |
| sf-slack | <risto.pejasinovic> thought* | 10:56 |
| sf-slack | <risto.pejasinovic> Its very early draft | 10:57 |
| sf-slack | <mgielda> it's Yosys | 11:01 |
| sf-slack | <mgielda> I can see it indeed, but we I don't get a notification | 11:01 |
| sf-slack | <mgielda> so it's best to say explicitly when you're uploading stuff, and generally keep the conversation running | 11:02 |
| sf-slack | <mgielda> people are busy, they will not have time to ping you for updates | 11:02 |
| sf-slack | <mgielda> well you still have time to improve the proposal if you want to participate | 11:02 |
| sf-slack | <risto.pejasinovic> I am interested in project. You can see my line of thinking in proposal, maybe suggest me if I am far of? There are some details that I think I could n ot figure alone in proposal. It would take me probably a week or more to research. | 11:05 |
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| sf-slack | <risto.pejasinovic> I am not sure what fuzzers are all gonna be needed to document PS7 ports. So I cannot write for sure that... | 11:08 |
| sf-slack | <mgielda> well do as much reasearch as you can | 11:12 |
| sf-slack | <mgielda> we'll try to comment on your draft today | 11:12 |
| sf-slack | <mgielda> but don't sit around and wait, dig into the code | 11:13 |
| sf-slack | <mgielda> ;) | 11:13 |
| sf-slack | <risto.pejasinovic> Thanks, im on it :) . | 11:14 |
| sf-slack | <acomodi> @risto.pejasinovic a suggestion would be not to write only the links of the github issues, but try also to briefly explain what they are about, this will increase readability of the document. | 11:14 |
| sf-slack | <risto.pejasinovic> @acomodi Thanks, I will change that. | 11:15 |
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| duck2 | mgielda: hello, here is my draft: https://docs.google.com/document/d/1bxVSlnD2vfiWvrIwesxh0HMK4LLZORN8s4ZDm8yQ5WY/ I consider it to be mostly done(thanks to mithro's helpful comments), but I think there are a few things that I couldn't fully ...substantiate, such as the idea of generating the rr_graph from tileconn.json in VPR. i also didn't provid | 11:42 |
| duck2 | e a very exact schedule, but i feel that is against the nature of the job. anyway, comments are always welcome :) | 11:42 |
| tpb | Title: GSoC Proposal: Optimization of VPR File Formats - Google Docs (at docs.google.com) | 11:42 |
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| sf-slack | <saisumanthkalluri> Hello! I'm wishing to work on the issue #11 titled 'adding Verilog Support for Sphinx' and I wanted to know if building a Verilog Extension for Sphinx would be an appropriate amount of work for the GSoC project. I'm unable to make a much more educated decision as I discovered this project too late and I have started digging into the working of Sphinx but I'm running out of time. Thank you. | 12:21 |
| sf-slack | <saisumanthkalluri> (extension => domain) | 12:22 |
| sf-slack | <kgugala> Hi @saisumanthkalluri I think this could be a GSoC project | 12:23 |
| sf-slack | <saisumanthkalluri> @kgugala that's motivating! Although I do not think I have enough time left to break down the project deliverables to fine details without understanding Sphinx better (for which I have no time left). Would that be a big no-no as far as the selection process is concerned? I believe I have the skills though. | 12:25 |
| sf-slack | <kgugala> If you file a proposal draft we can help you with it | 12:27 |
| sf-slack | <kgugala> just ping as here | 12:27 |
| sf-slack | <saisumanthkalluri> @kgugala on it. thank you! | 12:28 |
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| sf-slack | <risto.pejasinovic> @acomodi I updated the draft with your suggestions. Can you take a look again. I am a bit worried about my predictions on complexity of individual tasks. | 14:55 |
| sf-slack | <mkurc> Good time of day. My status: Working on tile grid location mapping. After merging recent changes from master to my work I have a regression. The VPR cannot find a connection between CLBs and new synthetic BLK_SY-VCC and BLK_SY-GND tiles. Trying to locate the bug. | 14:57 |
| litghost | mkurc: Is it between VCC/GND and OPAD? | 15:41 |
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| mithro | duck2: It is expected that your schedule will probably change substantially when you actually get around to doing the implementation | 15:47 |
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| mithro | duck2: I'll put some more details into the Python about how to do the edge bit | 15:51 |
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| litghost | mkurc: https://github.com/SymbiFlow/symbiflow-arch-defs/issues/544 | 16:23 |
| tpb | Title: [XC7] Constant routing network cannot connect to OPADs · Issue #544 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 16:23 |
| litghost | mithro: https://github.com/SymbiFlow/symbiflow-arch-defs/pull/545 | 16:43 |
| tpb | Title: [XC7] Make use of global constant network optional. by litghost · Pull Request #545 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 16:43 |
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| sf-slack | <mkurc> @litghost No it is not to/from an OPAD | 17:43 |
| litghost | mkurc: Okay, then it is some other form of regression | 17:43 |
| sf-slack | <mkurc> This must be my mistake as the new constant routing works from master. | 17:44 |
| litghost | mkurc: You can try disabling the constant network per https://github.com/SymbiFlow/symbiflow-arch-defs/pull/545, but that isn't a long term solution | 17:44 |
| sf-slack | <mkurc> I've encountered the problem while merging my grid loc mapping with the master. | 17:45 |
| sf-slack | <mkurc> It works when the mapping is 1 to 1 (identical) but fails when I split CLB columns. | 17:45 |
| sf-slack | <mkurc> Probably there is something in the new code that I am missing. I am going to investigate tomorrow | 17:46 |
| litghost | k | 17:46 |
| sf-slack | <acomodi> equivalence tiles update: I have started implementing the solution described in the document. It seems to be working, with some workarounds, but I know how to get to a cleaner implementation. | 17:59 |
| litghost | acomodi: Great! | 18:00 |
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| Prayas | Hi All! This is Prayas. I am here to contribute to Symbiflow. | 18:53 |
| Prayas | I have some experience in this domain as I am an intern at Mentor-A Siemens usiness | 18:54 |
| Prayas | Business* | 18:55 |
| Prayas | I also have a Full Time offer there. I have experience in Design Verification Technology. I've worked on Unified Power Format and developed Power Aware APIs for Questa. | 18:58 |
| Prayas | The Questa® Advanced Simulator combines high performance and capacity simulation with unified advanced debug and functional coverage capabilities for the most complete native support of Verilog, SystemVerilog, VHDL, SystemC, SVA, UPF and UVM. | 18:58 |
| Prayas | The Questa Advanced Simulator is the core simulation and debug engine of the Questa Verification Solution; the comprehensive advanced verification platform capable of reducing the risk of validating complex FPGA and SoC designs. | 18:59 |
| Prayas | I'm exploring some symbiflow projects. Please let me know if you have some advice for me. If you think there is something I can start working on, please let me know. Will be happy to contribute in the future :) | 19:02 |
| Prayas | Also, I'm comfortable in system verilog. I can work on optimizations. I can also dump design hierarchyand library information into TCL files. | 19:03 |
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| Prayas | Hi All! | 19:56 |
| [itchyjunk] | Yes, your message appears, Prayas. | 19:57 |
| [itchyjunk] | You might need to wait for someone to respond if you asked a question.Good luck. | 19:57 |
| Prayas | Thanks @itchyjunk | 19:57 |
| Prayas | I just registered my nickname. I don't know if my messages were visible here not. So, sending them again. Please ignore them, if its spam for you. | 19:58 |
| Prayas | Hi All! This is Prayas. I am here to contribute to Symbiflow. | 19:59 |
| Prayas | I have some experience in this domain as I am an intern at Mentor-A Siemens Business | 19:59 |
| Prayas | I have experience in Design Verification Technology. I've worked on Unified Power Format and developed Power Aware APIs for Questa. | 19:59 |
| Prayas | The Questa® Advanced Simulator combines high performance and capacity simulation with unified advanced debug and functional coverage capabilities for the most complete native support of Verilog, SystemVerilog, VHDL, SystemC, SVA, UPF and UVM. | 19:59 |
| Prayas | I'm exploring some symbiflow projects. Please let me know if you have some advice for me. If you think there is something I can start working on, please let me know. Will be happy to contribute in the future :) | 20:00 |
| Prayas | Also, I'm comfortable in system verilog. I can work on optimizations. I can also dump design hierarchyand library information into TCL files. | 20:00 |
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| [itchyjunk] | https://symbiflow.github.io/#help | 20:04 |
| tpb | Title: SymbiFlow - the GCC of FPGAs (at symbiflow.github.io) | 20:04 |
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| [itchyjunk] | Prayas_, not sure if you saw it. but following the topic, i found this link | 20:09 |
| [itchyjunk] | https://symbiflow.github.io/#help | 20:09 |
| tpb | Title: SymbiFlow - the GCC of FPGAs (at symbiflow.github.io) | 20:09 |
| sf-slack | <arora.prayas> Thanks | 20:12 |
| [itchyjunk] | Oh, I was going to suggest checking slack but looks like there is a bridge already. | 20:16 |
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| Prayas_ | Yes, thanks :) | 20:26 |
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| sf-slack | <arora.prayas> Hi! I'm looking to work on the issue #16 - 'Convert the Verilog to Routing test runner from Perl to Python' (link- https://github.com/SymbiFlow/ideas/issues/16 ). I have a query, what is the expected approach for this task ? Should I write suitable regex to convert some I wanted to know if building a Verilog Extension for Sphinx would be an appropriate amount of work for the GSoC project. I'm unable to make a | 20:37 |
| sf-slack | much more educated decision as I discovered this project too late and I have started digging into the working of Sphinx but I'm running out of time. Thank you. | 20:37 |
| tpb | Title: Convert the Verilog to Routing test runner from Perl to Python · Issue #16 · SymbiFlow/ideas · GitHub (at github.com) | 20:37 |
| sf-slack | <arora.prayas> Hi! I'm looking to work on the issue #16 - 'Convert the Verilog to Routing test runner from Perl to Python' (link- https://github.com/SymbiFlow/ideas/issues/16 ). I can work on both Perl and Python as I have done some scripting before. I have a query. What is the expected approach for this task? Is there some common code in similar scripts that I can write suitable regular expressions for to convert it to Python | 20:44 |
| sf-slack | ? The other way would be to understand the perl scripts and write equivalent Python scipts. Will this be a good project to be considered for my GSOC '19 application ? Regards, Prayas Arora | 20:44 |
| tpb | Title: Convert the Verilog to Routing test runner from Perl to Python · Issue #16 · SymbiFlow/ideas · GitHub (at github.com) | 20:44 |
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| Simian | Hey all | 20:52 |
| Simian | Does anyone have an example of an ICE40 fasm | 20:53 |
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| litghost | https://usercontent.irccloud-cdn.com/file/5sIghAPd/top.fasm | 21:11 |
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| hackerfoo | Do the autosim targets work in symbiflow-arch-defs? I tried running ram_test_autosim_synth_view, but the clock runs and nothing else happens. | 22:33 |
| mithro | hackerfoo: Unclear | 22:34 |
| litghost | @hackerfoo: The DRAM one might work | 22:34 |
| hackerfoo | That was the DRAM one. | 22:34 |
| litghost | @hackerfoo: I remember it working okay, and I think I debugged it using autosim | 22:35 |
| litghost | hackerfoo: But its been a while | 22:35 |
| * hackerfoo uploaded an image: autosim.jpg (306KB) < http://sandbox.hackerfoo.com:8008/_matrix/media/v1/download/sandbox.hackerfoo.com/YrMShHMdcNkGQHpanFkWxHFo > | 22:35 | |
| hackerfoo | mem[63:0] is stuck at a bunch of 6s and 9s. | 22:36 |
| litghost | hackerfoo: Ya, I see that | 22:37 |
| litghost | hackerfoo: Did you look at the FSM state signals | 22:37 |
| hackerfoo | Those are the only signals that had names. I couldn't find the others in the wave viewer. There are a bunch of numbers of the form _NNNN_. | 22:40 |
| elms | Anyone familiar with or know about https://www.efinixinc.com/technology.html ? | 22:45 |
| litghost | hackerfoo: Click the "top" to see the signal names | 22:46 |
| litghost | hackerfoo: The sim does appear to be broken, which is very interesting. Likely a sim model error | 22:47 |
| hackerfoo | Thanks. I see lots of signals with Xs now. | 22:49 |
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| hackerfoo | It seems to get stuck in VERIFY_INIT state. | 22:57 |
| hackerfoo | Should I create an issue? | 23:01 |
| litghost | hackerfoo: Sure | 23:02 |
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