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| mithro | litghost: What is the ratio between edges and nodes that you have seen? | 00:13 |
|---|---|---|
| litghost | mithro: Right now 1:5 | 00:13 |
| litghost | mithro: But it varies | 00:13 |
| mithro | litghost: Do you have a simple example with rr_graph metadata? | 00:39 |
| litghost | mithro: Like an XML? | 00:40 |
| mithro | litghost: yeah | 00:40 |
| mithro | litghost: Have you seen this structure before? | 01:40 |
| mithro | https://www.irccloud.com/pastebin/qAPbnE7i/ | 01:40 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 01:40 |
| mithro | Hadn't seen `map(EmployeeRecord._make, cursor.fetchall())` before... | 01:41 |
| litghost | mithro: Ya, but it would be of very limited value. The amount of ORM'ing in the xc7 import is very small | 01:41 |
| litghost | mithro: Most of the SQL is purely relational | 01:41 |
| mithro | litghost: you mentioned that just generation of the tuples / named tuples was taking significant time? | 01:42 |
| litghost | mithro: Ya, but the solution was to just skip generating the named tuple at all | 01:42 |
| mithro | litghost: Should the artix7/mask_clk_hrow_bot_r.db still exist? | 01:50 |
| litghost | Yes | 01:50 |
| mithro | litghost: It's not being generated... | 02:08 |
| mithro | litghost: The patch file looked strange :-P -> https://github.com/SymbiFlow/prjxray/pull/710 | 02:43 |
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| sf-slack1 | <mkurc> The most up-to-date Yosys on Symbiflow repo does not infer BRAM (or other type of memory) correctly. It should do when defining an array in verilog and initializing it using `initial` statemets. I've created an issue: https://github.com/SymbiFlow/yosys/issues/17 | 13:45 |
| tpb | Title: Yosys cannot infer BRAM correctly on current master+wip · Issue #17 · SymbiFlow/yosys · GitHub (at github.com) | 13:45 |
| sxpert | have something related, Warning: Replacing memory \hex with list of registers. See saturn_debugger.v:152 | 13:47 |
| sxpert | hex is an array of bytes, should be a couple of 16x4 distributed rams | 13:48 |
| daveshah | mkurc: Does it work if you revert https://github.com/YosysHQ/yosys/pull/843/commits/7cfae2c52fb8e210a68032a109646785e4353dcc ? | 14:06 |
| tpb | Title: Use mem2reg on memories that only have constant-index write ports by cliffordwolf · Pull Request #843 · YosysHQ/yosys · GitHub (at github.com) | 14:06 |
| daveshah | sxpert: in any case, a ROM will never be mapped to distributed RAM, as it is more efficient just to use LUTs | 14:07 |
| daveshah | sxpert: although I think it triggers this bug too, your case will always end up as LUTs | 14:07 |
| sf-slack1 | <mkurc> Yeah, I've stumbled upon the problem while trying to place program memory for Picosoc in BRAM. I always ended up with it in LUTs. | 14:09 |
| sf-slack1 | <mkurc> I'll check that commit | 14:09 |
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| sf-slack1 | <mkurc> @sxpert You are right. The PR #843 to YosysHQ changes the behavior and the memory is no longer inferred when it is a ROM. | 14:18 |
| daveshah | Probably best if you create a GitHub issue upstream with your testcase | 14:20 |
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| sf-slack1 | <mkurc> @daveshah https://github.com/YosysHQ/yosys/issues/867 | 15:40 |
| daveshah | Thanks | 15:40 |
| daveshah | seems to be 404? | 15:41 |
| sxpert | same here | 15:41 |
| sxpert | just appeared | 15:43 |
| sxpert | but only in the issue list | 15:43 |
| daveshah | Working for me now | 15:43 |
| sf-slack1 | <mkurc> Posted the file again in a comment | 15:43 |
| sxpert | ah there | 15:44 |
| sxpert | guess it takes some time to replicate within github's infrastructure | 15:44 |
| daveshah | mkurc: if you are curious, the main purpose of #843 was to fix cases where an array was being used as an array of signals rather than a memory, rather than as an optimisation per se | 15:44 |
| daveshah | I think the solution will be to not apply it where the constant writes are in an initial | 15:44 |
| sf-slack1 | <mkurc> Ok, I see. | 15:49 |
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| mithro | @mkurc: Did my comment on vtr #17 make sense? | 16:52 |
| sf-slack1 | <mkurc> @mithro Yes, it does. | 16:53 |
| mithro | mkurc: So the two things should be implemented without interacting with each other | 16:53 |
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| sf-slack1 | <mkurc> Right, now it is clear for me | 16:54 |
| mithro | The pip fuzzers seem to have been really flaky lately? | 16:56 |
| mithro | litghost: The .patch file seems to be working okay! | 17:01 |
| mithro | litghost: https://console.cloud.google.com/storage/browser/symbiflow-prjxray/artifacts/prod/foss-fpga-tools/prjxray/presubmit/database/zynq7/161/20190311-211723/database/ | 17:01 |
| tpb | Title: Google Cloud Platform (at console.cloud.google.com) | 17:01 |
| mithro | kgugala: Take a look at https://vtr-verilog-to-routing.readthedocs.io/en/latest/tutorials/timing_simulation/index.html | 17:22 |
| tpb | Title: Post-Implementation Timing Simulation Verilog-to-Routing 8.0.0-dev documentation (at vtr-verilog-to-routing.readthedocs.io) | 17:22 |
| mithro | acomodi: https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/478 | 17:24 |
| tpb | Title: WIP: Replicate fan out issue by litghost · Pull Request #478 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 17:24 |
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| duck2 | hello, now i hold ownership of one a7-35t | 17:57 |
| duck2 | as far as i understand, currently i cannot go from verilog-->yosys->vtr->prjxray-->this device, right? vivado has to step in somewhere | 17:58 |
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| litghost | duck2: No, prjxray-db has the required inputs (which do currently come from vivado) | 18:05 |
| litghost | duck2: Assuming you are using a basys3. If you want different pins or a different layout, then yes, Vivado is required. | 18:05 |
| duck2 | what i have is a smaller thing called cmod a7. maybe stupid question but where do pin assignments come into play in the flow? in vtr arch def? | 18:13 |
| litghost | duck2: Okay, if you have different board you will need a new "harness", which does required vivado. | 18:14 |
| litghost | duck2: Harness generation is here: https://github.com/SymbiFlow/prjxray/tree/master/minitests/roi_harness | 18:15 |
| tpb | Title: prjxray/minitests/roi_harness at master · SymbiFlow/prjxray · GitHub (at github.com) | 18:15 |
| litghost | duck2: Make a new file like this one https://github.com/SymbiFlow/prjxray/blob/master/minitests/roi_harness/basys3.sh | 18:15 |
| tpb | Title: prjxray/basys3.sh at master · SymbiFlow/prjxray · GitHub (at github.com) | 18:15 |
| litghost | duck2: And add a case in https://github.com/SymbiFlow/prjxray/blob/master/minitests/roi_harness/runme.tcl#L153 | 18:15 |
| tpb | Title: prjxray/runme.tcl at master · SymbiFlow/prjxray · GitHub (at github.com) | 18:15 |
| litghost | duck2: FYI, we are relatively close to no longer needing the ROI harness, maybe 1 or 2 months? | 18:16 |
| litghost | duck2: If you are interested in helping with removing the need for the ROI harness, I can point you at issues required to remove the harness. | 18:16 |
| duck2 | i think i saw the issues while exploring but had a hard time understanding why is a harness needed | 18:20 |
| duck2 | is it so we generate the bitstream for the part we know about and place it inside a "general" bitstream generated by vivado? | 18:20 |
| litghost | duck2: Two reasons, IOBs and CLK trees | 18:21 |
| litghost | duck2: We are missing some segbits for CLKs, are missing synthesis of both IOBs and CLK trees, and do not have place and route support for IOBs and CLK trees | 18:21 |
| litghost | duck2: The ROI harness handles these things | 18:21 |
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| litghost | duck2: We are not missing many segbits for CLKs, roughly the 9 or so bits identified in https://github.com/SymbiFlow/prjxray/issues/684 | 18:22 |
| tpb | Title: Document all bits used in the basys3 SWBUT ROI · Issue #684 · SymbiFlow/prjxray · GitHub (at github.com) | 18:22 |
| litghost | duck2: Once those bits are documented, then arch defs for the IOB and CLK tree types need to be written, along with a sythesis step | 18:23 |
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| duck2 | i see. i would like to help, but i think first i should install vivado(had ise before) and try to make a harness for this device | 18:29 |
| duck2 | so that i have a better grasp of things | 18:29 |
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| duck2 | thx for the information^^ | 18:30 |
| litghost | duck2: Sure. I agree that having a harness is a good first step | 18:30 |
| litghost | FYI, you must use Vivado 2017.2 | 18:32 |
| duck2 | ok. is the webpack sufficient or do i need a full license? | 18:33 |
| litghost | webpack is fine | 18:39 |
| mithro | litghost: https://github.com/SymbiFlow/prjxray/pull/715 <- that should fix my issue with the hclk bits missing? | 18:48 |
| tpb | Title: Fix 048 not using correct directory. by litghost · Pull Request #715 · SymbiFlow/prjxray · GitHub (at github.com) | 18:48 |
| litghost | mithro: On a7, yes | 18:48 |
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| mithro | litghost: https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc7/utils/prjxray_create_edges.py is the code which creates the edges, right? | 21:15 |
| tpb | Title: symbiflow-arch-defs/prjxray_create_edges.py at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 21:15 |
| litghost | mithro: Yes | 21:15 |
| mithro | litghost: It's zynq not zync :-P | 21:22 |
| sxpert | zinc ? | 21:27 |
| mithro | litghost: Do you have a doc which explains the dataflow with the new sqlite process? It seems like you generate the edges into the `graph_edge` table? | 21:59 |
| litghost | mithro: You mean https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/utils/lib/connection_database.py#L16 | 22:00 |
| tpb | Title: symbiflow-arch-defs/connection_database.py at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 22:00 |
| mithro | litghost: Building channels is then done as part of the "mark_track_liveness"? | 22:00 |
| litghost | mithro: We only need channel ptc's for live channels | 22:01 |
| mithro | Live means a track which has a connection to another track? | 22:01 |
| litghost | mithro: Liveness should mean that it is possible to route on it | 22:02 |
| litghost | mithro: Liveness is mostly a ROI based concept | 22:02 |
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