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| mithro | litghost: https://github.com/SymbiFlow/prjxray-db/compare/master...mithro:master | 01:37 |
|---|---|---|
| tpb | Title: Comparing SymbiFlow:master...mithro:master · SymbiFlow/prjxray-db · GitHub (at github.com) | 01:37 |
| litghost | That looks good | 01:46 |
| mithro | litghost: Great! Pushed | 02:01 |
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| litghost | symbiflow-arch-defs can now place and route a working Murax (https://github.com/SpinalHDL/VexRiscv#murax-soc) on a basys3! TDP BRAM 18k are testing both 8 and 16bit wide! | 05:36 |
| tpb | Title: GitHub - SpinalHDL/VexRiscv: A FPGA friendly 32 bit RISC-V CPU implementation (at github.com) | 05:36 |
| litghost | Instructions are https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/soc_tests/murax/README.md | 05:37 |
| tpb | Title: symbiflow-arch-defs/README.md at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 05:37 |
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| sf-slack | <kgugala> litghost: this is absolutely awesome!! | 12:14 |
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| sorear | (can someone summarize exactly what the new development is? best guess: using only free tools, can build muraxsoc as a partial reconfiguration bitstream, still need vendor tools for the "outer" bitstream with I/Os) | 21:50 |
| litghost | Sorear: exat | 22:52 |
| litghost | Exactly | 22:52 |
| litghost | Next step is getting picosoc working | 22:52 |
| litghost | The IOB and clock network definition, to remove the outer bitstream | 22:53 |
| litghost | Then* | 22:53 |
| sorear | And the “new” part is … BRAMs? | 22:53 |
| litghost | From the outside, ya | 22:55 |
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