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| kgugala | Morning mithro | 08:51 |
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| mkurc | Morning | 11:57 |
| mkurc | I need some advice | 11:57 |
| mkurc | I am trying to migrate all VPR related stuff out of Yosys | 11:57 |
| mkurc | I want to have a common flow for Vivado and VPR up to some point: | 11:58 |
| mkurc | Verilog -> synthesis(yosys) -> edif -> Vivado | 11:59 |
| mkurc | and Verilog -> synthesis(yosys) -> techmap(in yosys) -> blif -> VPR | 11:59 |
| mkurc | The problem is that i need to map $alu to a chain of CARRY4 which are understandable by Vivado | 11:59 |
| mkurc | and it works | 12:00 |
| mkurc | However, I cannot map CARRY4 to a chain of CARRY0 + 3xCARRY which are understandable by VPR | 12:00 |
| mkurc | CARRY0 and CARRY have separate output ports for carry chain and fabric | 12:00 |
| mkurc | and the Vivado's CARRY4 does not. It only has a "general" output. I guess that Vivado infers it later (after loading EDIF netlist) whether to connect it to fabric or carry chain. | 12:01 |
| mkurc | So it seems that removing VPR stuff from Yosys completely is not possible. | 12:02 |
| mkurc | Either we will have some VPR stuff in Yosys or we implement inference of carry chain connections in VPR (right?) | 12:03 |
| mkurc | Also the CARRY4 does not allow direct control of the chain intialization mux. It must also be inferred in Vivado | 12:05 |
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| mkurc | I've confirmed that xc7/tests/counter does not work from latest master branch (4b66516). I've created a related issue on Github - #382 | 16:36 |
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| elms | litghost: I have a iCE40 fasm file https://gist.github.com/elmsfu/e5383b543934a58e6f376a9d133283c9 Please comment on the gist with any feedback. | 19:14 |
| tpb | Title: iCE40 FASM ยท GitHub (at gist.github.com) | 19:14 |
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