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| mithro | litghost: I don't think it makes sense to request my review on prjxray changes - I don't feel like I can give that meaningful review | 00:06 |
|---|---|---|
| mithro | elms / litghost: Has is the status on a FASM style guide? | 00:06 |
| mithro | I assume no progress? | 00:06 |
| litghost | mithro: I think no one can, so do your best. We need cross pollination on fuzzer reviewers, so try. | 00:07 |
| mithro | litghost: I think kgugala, elms and acomodi are definitely good candidates | 00:07 |
| litghost | For anyone who knows about FPGA clock trees, there are bits that appear to be set on 7 series interconnect ports that become active if a global clock network is enabled, even if the interconnect port is not used. I assume these are designed to improve clock performance. Do they have a technical name? I've found them in at least two places, the ports to the CLK_HROW tile and the bottom and top sides of the bipips in | 01:02 |
| litghost | CLK_BUFG_REBUF tile. | 01:02 |
| litghost | Basically something akin to a bit that is set if the port is touching an active global clock network | 01:02 |
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| mithro | litghost: That is a clock buffer / redriver ? | 02:02 |
| mithro | CLK_BUFG <-- Global clock buffer driver | 02:02 |
| litghost | BUFG_REBUF is a redriver | 02:03 |
| litghost | But there are also bits in the BUFG -> HCLK tile | 02:03 |
| litghost | It appears there is a redriver at every pip junction that is active | 02:05 |
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| mithro | litghost: From what I've seen on some parts clock trees you need to enable drivers to kinda of "terminate" a tree. IE You need to enable one more driver than you would expect. | 02:24 |
| mithro | litghost: Dunno if Xilinx uses anything like that | 02:25 |
| mithro | litghost: BTW If you don't mention my nick, the likelihood I respond is pretty low :-P | 02:27 |
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| kgugala | mithro: we need to update technology mappings in YOSYS | 07:25 |
| kgugala | we'll create issue for that in symbiflow | 07:25 |
| kgugala | actually it should be done there, because after we update YOSYS we'll need to update symbiflow so it still work with VPR | 07:26 |
| mithro | kgugala: I think litghost had started moving the tech mapping into the symbiflow-arch-defs repo | 07:27 |
| kgugala | actually he created an issue, but I think mkurc will attack this | 07:28 |
| kgugala | he's made some progress with YOSYS | 07:29 |
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| acomodi | I am going to work on this issue instead: https://github.com/SymbiFlow/prjxray/issues/134 | 08:59 |
| tpb | Title: The way sites are named in Tile.get_instance_sites is broken · Issue #134 · SymbiFlow/prjxray · GitHub (at github.com) | 08:59 |
| mkurc | I will work on: https://github.com/SymbiFlow/symbiflow-arch-defs/issues/294 | 09:04 |
| tpb | Title: Move VPR specific yosys tech maps into symbiflow-arch-defs · Issue #294 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 09:04 |
| mkurc | Can somebody point me out whether I should add additional pass to Yosys that will map output of the "Xilinx flow" to VPR (as suggested in comment to #294)? | 09:06 |
| mkurc | Or should I add the mapping in the VPR itself? | 09:06 |
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| litghost | mkurc: Pass is already added | 16:14 |
| litghost | https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc7/yosys/synth.tcl | 16:14 |
| tpb | Title: symbiflow-arch-defs/synth.tcl at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 16:14 |
| litghost | Start of VPR specific techmaps are https://github.com/SymbiFlow/symbiflow-arch-defs/tree/master/xc7/techmap | 16:14 |
| tpb | Title: symbiflow-arch-defs/xc7/techmap at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 16:14 |
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| mkurc2 | litghost: ok, i will look at this tomorrow. | 18:23 |
| litghost | Basically anything that is changing the yosys techmap from master to master+wip should either 1) move to symbiflow if possible 2) be toggled by the -vpr flag in the synth_xilinx workflow | 18:25 |
| mkurc2 | i was thinking about sth. like that: we have a synthesis flow that maintains yosys-vivado compatibility followed by another pass that maps its result to primitives cimpatible with vpr. | 18:27 |
| mkurc2 | Because we would like to have a point in the flow that is compatible both with vivado and vpr | 18:28 |
| mkurc2 | currently the -vpr switch results in a different flow | 18:29 |
| litghost | The carry chain is harder to deal with | 18:29 |
| litghost | not impossible | 18:29 |
| litghost | You'll have to emit a CARRY4 primative | 18:30 |
| litghost | CARRY4 is a vivado tech primative | 18:30 |
| litghost | And then we can techmap the CARRY4 down into VPR CARRY0 and CARRY primatives | 18:30 |
| mkurc2 | no, i managed to get it working with only MUXCY and XORCY | 18:31 |
| litghost | Ya, but that won't work with VPR | 18:31 |
| mkurc2 | yes, but | 18:31 |
| litghost | Like I said, you'll need to emit a CARRY4 | 18:31 |
| litghost | CARRY4 is the closest primative that both Vivado and VPR could handle | 18:32 |
| mkurc2 | if i add another pass to yosys i think i can map muxcy and xorcy to carry0 and carry | 18:32 |
| litghost | Don't think so | 18:32 |
| litghost | a CARRY0 is both a MUXCY and XORCY | 18:32 |
| litghost | You'd need to fuze them | 18:33 |
| mkurc2 | it can be done in yosys code | 18:33 |
| litghost | And you won't have knowledge of where the carry0 goes from a sea of MUXCY | 18:33 |
| litghost | e.g. C++? | 18:33 |
| mkurc2 | yes | 18:33 |
| litghost | That's total overkill | 18:33 |
| litghost | Just have the carry chain techmap emit a carry4, and then fracture it for VPR | 18:33 |
| mkurc2 | so you say it is better to go with carry4? | 18:34 |
| litghost | Absolutely | 18:34 |
| mkurc2 | ok, thanks | 18:34 |
| litghost | Trying to merge MUXCY and XORCY, and find the root of the chain in C++ is significantly more complicated than having the verilog group carry bits into groups of 4 and emitting a CARRY4 primative | 18:35 |
| litghost | The VPR techmap logic already knows where the 0th, 3rd, etc carry bit is and emits a CARRY0 | 18:35 |
| litghost | It is only a small leap from there to emitting a CARRY4 with bits 0-3, then CARRY4 with 4-7, etc | 18:36 |
| mkurc2 | yes, but what if we have eg. chain with length of 6? | 18:37 |
| litghost | Then inputs 6/7 of the 2nd CARRY4 are disconnected | 18:37 |
| mkurc2 | shall we emit a not fully used carry4? | 18:37 |
| litghost | Of course | 18:37 |
| mkurc2 | ok | 18:37 |
| litghost | That strategy keeps the synthesis between Vivado and VPR as close a possible with limited downsides | 18:38 |
| mkurc2 | I was thinking that by doing it using individual muxcy and xorcy we can have carry chains of length not being multiply of 4. Then we would not emmit partially occupied carry4 and the remaining logic could then became a part of another chain. | 18:40 |
| mkurc2 | actually xorcy cannot exist without muxcy | 18:41 |
| mkurc2 | there is no other thing that it can be connected to. | 18:42 |
| mkurc2 | Ok, thank you for the feedback. i will back to it tomorrow. bye | 18:43 |
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| mithro | Morning | 20:51 |
| mithro | elms / litghost: I was trying to figure out the right targets to run on the CI for symbiflow-arch-defs and got myself confused.... | 20:51 |
| mithro | elms / litghost: Is there targets which map to "all xc7" / "all ice40" / etc ? | 20:51 |
| litghost | You can cd into the directory and run all | 20:54 |
| litghost | and check I think | 20:54 |
| litghost | so "cd build/xc7/ && make <target>" | 20:54 |
| litghost | and that will only build 7-series | 20:54 |
| litghost | mithro: Currently "all_route_tests" is only used by targets in <root>/tests | 20:57 |
| litghost | But that would be the obvious target to attach things too | 21:03 |
| mithro | litghost: What should I be using for target? Just all? | 22:23 |
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