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| mithro | litghost: https://github.com/SymbiFlow/prjxray-db/compare/master...mithro:master?expand=1 <- That is the latest database generation | 01:21 |
|---|---|---|
| tpb | Title: Comparing SymbiFlow:master...mithro:master · SymbiFlow/prjxray-db · GitHub (at github.com) | 01:21 |
| mithro | litghost: There is something going on with the HCLK fuzzers | 01:23 |
| mithro | litghost: They don't seem to be running properly... | 01:24 |
| litghost | Is it just https://github.com/SymbiFlow/prjxray/issues/568 ? | 01:24 |
| tpb | Title: Parallel build does not build all the targets · Issue #568 · SymbiFlow/prjxray · GitHub (at github.com) | 01:24 |
| whatnick | mithro: which host board are you using for Xray fuzzing ? Looking at setting up the fuzzer , since I have the headless xilinix toolchain already. | 01:24 |
| litghost | If you re-run make at the fuzzer root? | 01:24 |
| litghost | whatnick: Fuzzing only requires vivado | 01:25 |
| mithro | whatnick: You don't really use a "board" for X-Ray | 01:25 |
| litghost | It's purely software | 01:25 |
| mithro | whatnick: If you want to *use* the toolchain to produce bitstreams for designs that is a totally different thing | 01:26 |
| whatnick | I have the headless toolchain set-up and taking space on my machine. Planning to put it to good use if possible. | 01:29 |
| whatnick | If it is to bitstream only and back analysis of that I can keep running that ... | 01:30 |
| whatnick | Is the input vhdl manually generated ? auto-generated by the fuzzer ? | 01:30 |
| mithro | whatnick: No VHDL involved here - do you mean Verilog? | 01:30 |
| whatnick | Again my lack of knowledge there .... off to read fuzzer flow ... | 01:31 |
| mithro | whatnick: What are you trying to do? | 01:31 |
| whatnick | https://prjxray.readthedocs.io/en/latest/db_dev_process/overview.html is right location | 01:31 |
| tpb | Title: Overview Project X-Ray documentation (at prjxray.readthedocs.io) | 01:31 |
| whatnick | Help out with mapping the xilinix board and get off the proprietary toolchain I have the Mimas board. From your talk it is mostly usable ? | 01:32 |
| mithro | whatnick: Most of the Mimas boards are Spartan 6 based. Do you have a Mimas A7 or an older Mimas / Mimas V2? | 01:33 |
| whatnick | I did the fupy build for it using the prop toolchain over pycon 2018, aiming to get x-ray to the point where I can do the same with OS chain. I have the V2 | 01:34 |
| mithro | whatnick: The V2 is a Spartan 6 based board. The Spartan 6 it is not supported by Project X-Ray or SymbiFlow at all | 01:35 |
| whatnick | Aaahh ... | 01:36 |
| whatnick | okay time to get a new board .. | 01:36 |
| mithro | whatnick: SymbiFlow is also not ready for doing FuPy stuff on any Xilinx board yet either | 01:36 |
| mithro | whatnick: Yosys+nextpnr works fine with FuPy on the iCE40 parts | 01:37 |
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| whatnick | I only have the flea for ecp5 and an ice40 stick .. | 01:39 |
| whatnick | stepping back the overall goal is to do high speed ADC + Maths on FPGA to capture instantenous AC power usage and appliance finger printing ... | 01:40 |
| whatnick | It does not have to support Fupy, but will make it easier to iterate ... | 01:40 |
| whatnick | I have some ice40 parts + ADC as well from Olimex .. | 01:41 |
| whatnick | https://www.olimex.com/Products/FPGA/iCE40/iCE40-ADC/open-source-hardware | 01:42 |
| tpb | Title: iCE40-ADC - Open Source Hardware Board (at www.olimex.com) | 01:42 |
| whatnick | and - https://www.olimex.com/Products/FPGA/iCE40/iCE40HX1K-EVB/open-source-hardware | 01:42 |
| tpb | Title: iCE40HX1K-EVB - Open Source Hardware Board (at www.olimex.com) | 01:42 |
| whatnick | but I don't think the 1K is big enough for Fupy | 01:42 |
| whatnick | This may be better - https://www.olimex.com/Products/FPGA/iCE40/iCE40HX8K-EVB/open-source-hardware | 01:43 |
| tpb | Title: iCE40HX8K-EVB - Open Source Hardware Board (at www.olimex.com) | 01:43 |
| mithro | whatnick: I suggest we move to the #timvideos channel as this isn't really symbiflow related | 01:47 |
| whatnick | Sure ... | 01:48 |
| whatnick | I was also working on getting the ECP5 I have going ... would that be relevant ? | 01:49 |
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| whatnick | daveshah: I have started working on the ECP5-25F sample here https://github.com/whatnick/prjtrellis/tree/master/examples/soc_fleafpga | 01:56 |
| tpb | Title: prjtrellis/examples/soc_fleafpga at master · whatnick/prjtrellis · GitHub (at github.com) | 01:56 |
| whatnick | Pulled the lpf file from the manufacturer sample | 01:56 |
| whatnick | Will need to make other relevant changes to account for 25F in makefile I assume, as well as openocd | 01:57 |
| whatnick | This "../../misc/basecfgs/empty_lfe5um5g-45f.config --textcfg $@ --um5g-45k" targets 45f | 01:59 |
| mithro | whatnick: Getting ECP5 stuff into the TimVideos LiteX-BuildEnv would be super cool, but again the #timvideos IRC channel would be the best place for that | 03:29 |
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| mithro | litghost: https://github.com/SymbiFlow/prjxray/issues/582 -- I'm pretty sure its an issue in the Makefile at https://github.com/SymbiFlow/prjxray/tree/master/fuzzers/100-dsp-mskpat but I don't understand the file enough to see what the problem is | 03:54 |
| tpb | Title: mask_dsp_l.db file seems to be invalid · Issue #582 · SymbiFlow/prjxray · GitHub (at github.com) | 03:54 |
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| OmniMancer | Is there a particular reason for the version of Vivado that the Project X-Ray readme.md says to install? | 08:39 |
| mithro | OmniMancer: Other versions don't wokr | 09:06 |
| mithro | litghost: Latest db build - https://github.com/SymbiFlow/prjxray-db/compare/master...mithro:master | 09:08 |
| tpb | Title: Comparing SymbiFlow:master...mithro:master · SymbiFlow/prjxray-db · GitHub (at github.com) | 09:08 |
| mithro | litghost: Any idea what is going on with the artix7/tile_type_BRAM_L.json file? | 09:12 |
| mithro | kgugala: Do you have any idea about the parallel make issue? | 09:18 |
| OmniMancer | What is the most reasonable way to install that version of Vivado? | 09:18 |
| mithro | OmniMancer: Download it from the Xilinx website and install it? | 09:22 |
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| kgugala | mithro: TBH I'm starting to suspect a make bug - there seems to be some kind a race condition between the targets generated with fuzzer macro | 10:13 |
| kgugala | *some kind of a race condition | 10:13 |
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| kgugala | I have random results in each run | 10:16 |
| mithro | I think we should make the output of the fuzzers more readable / less verbose so you can better understand what is actually going on | 10:38 |
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| kgugala | it is visible what is going on - some fuzzers were newer run | 10:52 |
| kgugala | no matter the fact that they are in the makefile | 10:52 |
| kgugala | for some reason make decided that those should not be run | 10:53 |
| kgugala | the missing part of the DB is because some fuzzer didn't have a chance to produce it | 10:53 |
| kgugala | this is why I suspect make itself | 10:54 |
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| sxpert | what would be the proper command lines to generate a basic design from a simple .v file | 11:04 |
| mithro | kgugala: Do you know how to run make in debug mode? | 11:12 |
| mithro | sxpert: Hrm? If your asking how to create a bitstream from a simple verilog file for an ice40 I recommend asking in the #yosys or ##openfpga channels | 11:13 |
| sxpert | ok | 11:14 |
| * sxpert heads there | 11:14 | |
| kgugala | mithro: yes, I know | 11:38 |
| kgugala | I'll check what is happening there | 11:39 |
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| litghost | mithro: > Any idea what is going on with the artix7/tile_type_BRAM_L.json file? => This is a symptom of https://github.com/SymbiFlow/prjxray/issues/134 | 18:11 |
| tpb | Title: The way sites are named in Tile.get_instance_sites is broken · Issue #134 · SymbiFlow/prjxray · GitHub (at github.com) | 18:11 |
| litghost | Basically the way we are extracting BRAM and DSP names from the specific to generic and generic to specific is broken | 18:11 |
| litghost | It's critical to fix, but it would be nice to do at some point | 18:12 |
| litghost | Sorry, it's not critical to fix | 18:47 |
| litghost | Opps | 18:47 |
| mithro | kgugala: Sounds like you deserve cake? | 23:10 |
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