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| whatnick | I will fork pjtrellis and work on a soc_fleafpga example | 00:01 |
|---|---|---|
| whatnick | what is the syntax of the LPF file ? | 00:03 |
| whatnick | will open ocd will be okay push with this - ecp5-versa5g.cfg ? | 00:04 |
| whatnick | Okay I will be back ... off to lunch | 00:04 |
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| * whatnick back | 01:38 | |
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| Ayana | hello | 02:48 |
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| Ayana | i got some job for fuzzing xadc in 35c3 but i got a bug in processing make | 02:50 |
| perillamint | https://pastebin.com/eLHJRv9z | 02:51 |
| tpb | Title: Traceback (most recent call last): File "/home/ayana/prjxray/fuzzers/033-mon- - Pastebin.com (at pastebin.com) | 02:51 |
| perillamint | While running XADC fuzzer, fuzzer failed to fuzz specimen 008 | 02:51 |
| perillamint | Does anyone know how we can resolve this error? | 02:53 |
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| OmniMancer | What software is actually required to be installed to attempt to target a xilinx series 7 FPGA with open source tools? | 04:11 |
| sorear | it is not currently possible to target a series 7 with open source tools only | 04:18 |
| sorear | there are a couple flows which use yosys in conjunction with ise or vivado | 04:18 |
| OmniMancer | There is some work ongoing for open place and route for artix 7? | 04:22 |
| sorear | yes | 04:35 |
| sorear | it WILL BE possible to use an entirely open flow | 04:35 |
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| OmniMancer | How may one help with Artix 7 documentation work? | 12:26 |
| sorear | documentation is mostly done, we need people to write place and route tools | 12:27 |
| OmniMancer | Ah | 12:28 |
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| OmniMancer | Is there anything where small incremental contribution is possible? | 12:57 |
| sorear | uh, some other people here have long lists of those | 13:02 |
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| OmniMancer | Ah, I shall hang around in here tomorrow then | 13:15 |
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| litghost | perillamint: That means none of the tags found a solution. Are you sure that ADC configuration bits were being toggled? Are you sure that tilegrid.json has a definition for the XADC tile? | 17:54 |
| litghost | OmniMancer: Depends on what you want to focus on. Right now there is work in BRAM, MMCM, IOB and XADC documentation. There is also a need to expand base addresses in tilegrid to include all tiles found in parts (python and tcl skills recommended). On the place and route side, there are not architectural models for MMCM, IOB or XADC (python, xml and C++ skills recommended). There is also a need to write tests for both | 17:57 |
| litghost | prjxray and symbiflow | 17:57 |
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| whatnick | ping daveshah, working out openocd profile for the LFE5U-25F | 22:27 |
| daveshah | hiya | 22:27 |
| daveshah | Best is to look for an existing profile for the fleafpga | 22:27 |
| sorear | OmniMancer: litghost replied, check https://logs.timvideos.us/%23symbiflow/latest.log.html near [17:57] | 22:28 |
| daveshah | The fleafpga uses a less common FTDI chip, iirc | 22:28 |
| OmniMancer | Thanks sorear | 22:28 |
| OmniMancer | daveshah: do you have any idea how different ECP3 series is from ECP5? | 22:28 |
| daveshah | By no means identical | 22:29 |
| daveshah | I had a quick look at a bitstream once and I remember a few commands at least being different | 22:29 |
| daveshah | Logic tiles look a bit different in terms of routing too | 22:30 |
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| whatnick | daveshah: we identified it from the schematic | 22:37 |
| whatnick | It has a FT230XQ for USB serial/JTAG | 22:39 |
| nats` | hey plop guyz :) | 22:39 |
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| whatnick | hey nats` | 22:49 |
| whatnick | i am just getting back into IRC land .. | 22:50 |
| whatnick | been too long in twitter oceans | 22:50 |
| whatnick | working on ECP5 FleaFpga | 22:50 |
| whatnick | Hopefully will have picorv soc on it soon ... | 22:50 |
| sorear | welcome! | 22:50 |
| daveshah | whatnick: so you'll need to first see if openocd supports that chip | 22:54 |
| daveshah | If it does, you'll need to create a config file with the correct pinout | 22:55 |
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