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| robarago | Hi to all. I would appreciate a hint from somebody who owns an ECP5 Versa. Anybody? | 17:37 |
|---|---|---|
| daveshah | Yes | 17:37 |
| robarago | Is this devboard good for FOSS development with prjtrellis? Any important issue? My main concern is if it would be possible to run GNU/Linux as a target OS in the FPGA. Do you know any project doing that? | 17:40 |
| daveshah | Yes, it's a nice board | 17:40 |
| daveshah | I have done this on a Versa, but there is no support in the open source tools for DDR3, so I added a hat for SDRAM | 17:41 |
| daveshah | The alternative is to use a ULX3S which has SDRAM on board | 17:41 |
| daveshah | https://twitter.com/fpga_dave/status/1059536850199678976 | 17:41 |
| robarago | Oh, very interesting. I was thinking to purchase the ECP5 because of the DDR3 module but of course I would like to use the open source toolchain... Thank you very much for the link | 17:42 |
| daveshah | There will be DDR3 support soon (Feb/March hopefully) | 17:43 |
| daveshah | The main issue is getting litedram ported and working out what primitives it needs | 17:43 |
| daveshah | we already have bitstream documentation needed for DDR3, just need to finish the place and route side of things | 17:43 |
| robarago | Oh, I could wait, of course. I'm happy to hear that. You're doing a great job | 17:44 |
| robarago | I like very much the ULX3s but it is available to purchase? | 17:46 |
| daveshah | Might be worth asking here: https://gitter.im/ulx3s/Lobby | 17:47 |
| tpb | Title: ulx3s/Lobby - Gitter (at gitter.im) | 17:48 |
| robarago | Thank you all very much for the info. Really helpful | 17:49 |
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| _florent_ | daveshah: i started porting litedram to ECP5 for DDR3, but it's a bit more work than i expected since we need to use a very specific structure for the IO primitives | 18:29 |
| _florent_ | daveshah: it's here: https://github.com/enjoy-digital/versa_ecp5_dram | 18:29 |
| tpb | Title: GitHub - enjoy-digital/versa_ecp5_dram (at github.com) | 18:29 |
| daveshah | _florent_: awesome | 18:30 |
| daveshah | That was my feeling once I started looking at the set of primitives too | 18:30 |
| _florent_ | daveshah: i'd like to continue working on it but have difficulties finding time for that... | 18:30 |
| daveshah | I'll see if I can play about a bit | 18:30 |
| _florent_ | for now, i just tried to instantiate the primitives to be able to route with diamond | 18:31 |
| daveshah | _florent_: just so we are on the same page, this is the error I get atm | 18:41 |
| daveshah | > ERROR - par: Based on physical connectivity, comp "DQSBUFM" has to be placed at site "LDQS29". However, it has been placed at site "LDQS41". This could be caused by a LOCATE preference.. | 18:41 |
| _florent_ | daveshah: yes i'm not sure it was able to finish place and route regarding my last comment ("almost able to p&r") | 18:42 |
| _florent_ | daveshah: btw, i was trying to follow TN1265 | 18:43 |
| daveshah | I'll take a look over the next few days | 18:43 |
| daveshah | Actually I think the trellis db might be useful insight to connectivity... | 18:44 |
| daveshah | I think the current error is because DQS is shared over all IO, whereas it should be per byte group | 18:44 |
| _florent_ | ok cool if you look at that | 18:44 |
| daveshah | OK, got it to build at least... | 18:59 |
| daveshah | https://github.com/daveshah1/versa_ecp5_dram/tree/fixes | 19:00 |
| tpb | Title: GitHub - daveshah1/versa_ecp5_dram at fixes (at github.com) | 19:00 |
| daveshah | I think the next step is actually to understand DQSBUFM a bit better... | 19:04 |
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| mithro | Morning everyone! | 20:32 |
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