| *** tpb has joined #symbiflow | 00:00 | |
| *** celadon_ has joined #symbiflow | 02:00 | |
| *** celadon has quit IRC | 02:07 | |
| *** citypw has joined #symbiflow | 03:29 | |
| *** _whitelogger has quit IRC | 04:36 | |
| *** _whitelogger has joined #symbiflow | 04:39 | |
| *** proteusguy has joined #symbiflow | 06:13 | |
| *** proteusguy has quit IRC | 06:29 | |
| *** proteusguy has joined #symbiflow | 06:45 | |
| *** _whitelogger has quit IRC | 08:03 | |
| *** _whitelogger has joined #symbiflow | 08:06 | |
| nats` | plop | 08:57 |
|---|---|---|
| *** celadon_ is now known as celadon | 09:29 | |
| *** citypw has quit IRC | 11:03 | |
| *** kraiskil has joined #symbiflow | 11:33 | |
| *** proteusguy has quit IRC | 12:58 | |
| *** proteusguy has joined #symbiflow | 13:31 | |
| *** JustAnother1 has joined #symbiflow | 13:52 | |
| *** citypw has joined #symbiflow | 14:03 | |
| nats` | hey cool litghost thanks for the merge :) | 15:23 |
| nats` | \o/ | 15:23 |
| nats` | my 7th commit | 15:23 |
| digshadow | fyi back from travels if anyone is waiting on me for something | 16:02 |
| *** kraiskil has quit IRC | 18:36 | |
| nats` | litghost, any thing I should do quickly ? | 19:10 |
| nats` | I can't remember what was the "road map" | 19:10 |
| litghost | Refactor 072 and 074 to share what is common | 19:10 |
| litghost | start with the flags we added to 074 | 19:10 |
| litghost | I refactored the post-processing, it's much faster now and uses less memory | 19:10 |
| litghost | so mostly just finish cleaning up 072/074 | 19:11 |
| nats` | oky I can move the pool in the utils.py ? | 19:13 |
| nats` | I need to add argument to 072 too | 19:13 |
| nats` | nothing else more important in short term ? | 19:13 |
| litghost | No, after that I'd say pick up something that interests you | 19:14 |
| litghost | We have plenty of the parts that are uninvestigate, XADC, MCMM, PCIE, IOB | 19:14 |
| litghost | BRAM too | 19:15 |
| litghost | https://github.com/SymbiFlow/prjxray/issues/477 | 19:15 |
| tpb | Title: BRAM interconnect muxes are missing · Issue #477 · SymbiFlow/prjxray · GitHub (at github.com) | 19:15 |
| nats` | litghost, where should I start when i'll do that ? because I don't even know how you "invetigated" | 19:22 |
| nats` | but I'm interested in MMCM because I tinkered a lot with it on artix | 19:22 |
| litghost | digshadow is a better person to talk with. However they already started the MMCM, so maybe that will provide enough of a hint. | 19:23 |
| litghost | https://github.com/SymbiFlow/prjxray/tree/master/fuzzers/031-cmt-mmcm | 19:24 |
| tpb | Title: prjxray/fuzzers/031-cmt-mmcm at master · SymbiFlow/prjxray · GitHub (at github.com) | 19:24 |
| litghost | I haven't taken a look at the state of the MMCM, but we are looking for two things | 19:24 |
| litghost | 1) Can all of the MMCM parameters be expressed by the segbits output from the fuzzers? | 19:24 |
| litghost | 2) Is there an MMCM specific routing that needs a fuzzer? | 19:24 |
| digshadow | 2 yes I think | 19:25 |
| litghost | 1) is an exercise in comparing https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/7series_hdl.pdf for the MMCM against the output from the fuzzer | 19:25 |
| digshadow | But 50 is pretty generic. We might be able to cover using it | 19:25 |
| litghost | It's also worth noting that the MMCM fuzzer is not part of the root make, so at a minimum adding it to the root Makefile and check the fuzzer for stability issues is useful work | 19:27 |
| litghost | Once 1) and 2) is done, then it needs to be added to symbiflow-arch-defs | 19:27 |
| litghost | BRAM example of doing this is here: https://github.com/SymbiFlow/symbiflow-arch-defs/pull/321 | 19:27 |
| tpb | Title: WIP: Initial XC7-BRAM support in VPR. by litghost · Pull Request #321 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 19:27 |
| nats` | oky :) | 19:35 |
| nats` | I'll annoy digshadow after fixing 072/074 :) | 19:35 |
| digshadow | nats`: ping me once you are ready. In the meantime I'll check in with the mmcm guy | 19:37 |
| mithro | Morning everyone | 20:23 |
| mithro | litghost: Do you need me to look at anything? | 20:23 |
| litghost | mithro: Not at this time | 20:27 |
| litghost | FYI, pushing a database update for artix7/kintex7 is a good plan | 20:27 |
| litghost | zync7 is close, but I heard from kgugala that fuzzer 058 failed | 20:28 |
| litghost | however that might be the last zync7 failure before an initial zync DB can be published | 20:28 |
| nats` | https://github.com/SymbiFlow/prjxray/commits/master <= litghost I was syncing my repo and I saw something weird in commit my 074 commit seems to have been applied two time oO | 20:36 |
| tpb | Title: Commits · SymbiFlow/prjxray · GitHub (at github.com) | 20:36 |
| nats` | uhhmm is it me or when i source the env now I don't have (env) prefix int he terminal anymore | 20:42 |
| nats` | that was pretty usefull | 20:43 |
| *** mario_ has joined #symbiflow | 20:44 | |
| nats` | litghost, I'm updating the 072 to be like 074 PR that and only after i'll split the pool function I would like to have functionnal block in case we need to rollback | 20:48 |
| litghost | sounds good | 20:49 |
| litghost | I only see the 074 once? | 20:49 |
| nats` | you have my commit | 20:50 |
| nats` | and then upper there is your commit saying merging PR | 20:50 |
| litghost | are you referencing to the merge commit (https://github.com/SymbiFlow/prjxray/commit/4efea261ddb6d279847a7299da7c8876d79b8271) | 20:50 |
| tpb | Title: Merge pull request #526 from natsfr/master · SymbiFlow/prjxray@4efea26 · GitHub (at github.com) | 20:50 |
| nats` | maybe i don't understand what that means | 20:50 |
| nats` | yes | 20:50 |
| litghost | github creates a merge commit when pulling PR's | 20:50 |
| litghost | that's all | 20:50 |
| nats` | ah oky | 20:51 |
| *** kraiskil has joined #symbiflow | 20:51 | |
| mario_ | Hello lads, at 35c3 I've seen your talk and waving for help and just listened to the interview on the hackaday podcast. And (i think tim was it) said it on 35c3 and the interview said that people with an spartan-6 would be cool to help documenting the bitstream. I do have a cheap chinese fpga board from ebay with a spartan-6 xc6slx9 on it. Is it possible for me to help porting that or is it even worth it? | 20:57 |
| mario_ | I only got into fpgas last semester, but it really got me and I think i want to learn more about them | 20:57 |
| sorear | there are I think 3 semi-active projects to study s6. hardware doesn't really help here, most of the process is feeding thousands upon thousands of verilog designs into ISE and correlating the input with the resulting bitstreams | 21:04 |
| mario_ | Is there any point where i can read up more on this or is this https://github.com/SymbiFlow/prjxray the best place? | 21:13 |
| tpb | Title: GitHub - SymbiFlow/prjxray: Documenting the Xilinx 7-series bit-stream format. (at github.com) | 21:13 |
| sorear | i'd say your best bet is to ask random people on here | 21:14 |
| mario_ | Okay thank you. My head can't handle that right now, but i hope in a few days/weeks. Just gotta get my head straight again | 21:17 |
| nats` | maybe we should add (env target) in the terminal prompt when sourced it could help I always wonder which terminal is sourced | 21:17 |
| sorear | maybe mwk | 21:18 |
| nats` | mwk ? | 21:19 |
| sorear | IRC user, posted a s6 thing recently | 21:20 |
| nats` | ah sorry didn't see you were discussing with mario_ | 21:21 |
| *** mario_ has quit IRC | 21:36 | |
| mithro | sorear: I actually think the s6 stuff is mostly blocked behind someone doing -> https://github.com/YosysHQ/yosys/issues/448 | 22:23 |
| tpb | Title: Spartan 3/6 support with ISE backend? · Issue #448 · YosysHQ/yosys · GitHub (at github.com) | 22:23 |
| nats` | mithro, I saw a new project poped recently in my github feed | 22:26 |
| nats` | can't find it... I should have followed it | 22:32 |
| nats` | I have a weird fail in "make format" | 22:38 |
| nats` | if [ -e env/bin/activate ]; then . env/bin/activate; fi; find . -name \*.py -and -not -path './third_party/*' -and -not -path './.git/*' -and -not -path './env/*' -and -not -path './build/*' -print0 | xargs -0 -P $(nproc) yapf -p -i | 22:38 |
| nats` | xargs: yapf: No such file or directory | 22:38 |
| nats` | Makefile:52: recipe for target 'format-py' failed | 22:38 |
| nats` | make: *** [format-py] Error 127 | 22:38 |
| *** kraiskil has quit IRC | 22:40 | |
| mithro | nats`: make env ? | 22:40 |
| mithro | nats`: What was the project about? | 22:41 |
| nats` | about an open source toolchain for xilinx serie 6 and 3 | 22:41 |
| nats` | the author has an eastern europe name if I remember correctly | 22:41 |
| nats` | I never run make env | 22:42 |
| nats` | ahhh you're right | 22:42 |
| nats` | I erased my repo to clean it that's why :) | 22:43 |
| nats` | thanks | 22:43 |
| mithro | There are a bunch of bitstream stuff for Xilinx s6 | 22:44 |
| mithro | but the missing part is the synthesis + place and route | 22:45 |
| nats` | mithro, https://github.com/koriakin/prjleuctra | 22:45 |
| tpb | Title: GitHub - koriakin/prjleuctra: Reverse engineering tools and chip database for ISE-era Xilinx FPGAs. (at github.com) | 22:45 |
| mithro | nats`: Oh, interesting - they seem to have an approach for generating the tiles which is somewhere I think SymbiFlow might be heading.... | 22:51 |
| nats` | apparently the guy is inspired by prjxray | 22:52 |
| nats` | it quote it in readme | 22:52 |
| nats` | litghost, https://github.com/SymbiFlow/prjxray/pull/555 <= I made the same change to add argument to the 072 fuzzer, if you could do a run to compare output that would be cool :) | 22:53 |
| tpb | Title: Adding modular arguments for parallel Fuzzer 072 by natsfr · Pull Request #555 · SymbiFlow/prjxray · GitHub (at github.com) | 22:53 |
| nats` | he sha1 smart I forgot that -_- | 22:53 |
| nats` | let me few minutes to regenerate it and compare | 22:54 |
| mithro | nats`: Yeah | 22:54 |
| mithro | nats`: Still the big part that is missing is the Yosys side... | 22:55 |
| nats` | to be honnest I still don't know the general architecture of this project :) | 22:55 |
| mithro | nats`: https://usercontent.irccloud-cdn.com/file/zziYOZqG/image.png | 22:58 |
| nats` | sure I saw that but I don't understand why S6 couldn't be supported by Yosys after reverse | 22:59 |
| litghost | It can, but someone has to do that work | 23:00 |
| daveshah | Support in Yosys is orthogonal to bitstream stuff | 23:01 |
| daveshah | I'm pretty sure s6 did work to some extent in Yosys once, although maybe there has been bitrot | 23:01 |
| nats` | uhhmm the PNR needs to be tuned to target ? | 23:01 |
| litghost | Yosys doesn't do PNR, it does synthesis | 23:02 |
| nats` | uhh sure it's logic in fact | 23:02 |
| nats` | synthesis and PnR needs that | 23:02 |
| nats` | oky I think I get the idea | 23:02 |
| nats` | if we start a work on Serie 6 and 3 I would certainly help but I don't like those serie they have so many flaws | 23:03 |
| daveshah | Synthesis just needs to know about the primitives | 23:03 |
| nats` | the serie 7 seems perfect in comparison :) | 23:03 |
| daveshah | And in general the vendors document them reasonably well | 23:03 |
| nats` | ok :) | 23:03 |
| nats` | so basically you're saying a lot of work need to be done on a part with no reverse and "only" writing the good interface in Yosys | 23:04 |
| nats` | ? | 23:04 |
| litghost | Yes and no. Implementing the techlibs are the first step. Lowering the synthesized output then may require further mapping for the PnR tooling. For example DRAM primatives can be considered multiple placable units | 23:06 |
| nats` | oky I get the idea | 23:07 |
| mithro | nats`: bitstream documentation for the s6 is not currently the long pole for s6 support. Someone needs to do the work in Yosys first and then PnR.... | 23:09 |
| nats` | I would like to help but I'm really too ignorant for that :) | 23:09 |
| *** Rahix has quit IRC | 23:22 | |
| nats` | litghost, I apparently have a problem sha1 is not the same ! | 23:59 |
| nats` | I'm surprised i'll check why | 23:59 |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!
