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| felix_ | Bertl_oO: on the testing: will it be helpful for you if i make a test design that blinks the leds (to test the general circuitry) and then a loopback design that loops back the serial port and the lvds lanes? that should be an easy thing to do and i probably could do that this weekend | 11:47 |
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| felix_ | a real test for the clocking chip and the sdi chips is more work and i definitely won't get to work on that before maybe next tuesday | 11:48 |
| Bertl_oO | I've designed (and built) a breakout board which basically breaks out all the dual plugin connections | 13:21 |
| Bertl_oO | so it is for example easy to put jumpers on the LVDS pairs to see if they have a connection | 13:21 |
| Bertl_oO | we won't have the SDI chips on first hardware test (you requested the FPGA only, IIRC) | 13:22 |
| Bertl_oO | so testing for those doesn't make much sense anyway, but it wouldn't hurt to output some kind of signal on the MGTs so that I can verify connectivity before we add the SDI chips | 13:23 |
| felix_ | ah, yeah, not populating the sdi chips is better | 13:23 |
| Bertl_oO | in general, test signals on all relevant connections are a good idea, so that they can be probed with a scope | 13:24 |
| Bertl_oO | I usually send a serial (UART style) sequence which encodes the pin | 13:24 |
| Bertl_oO | if that is sent one pin at a time, it is easy to spot unwanted connections too | 13:25 |
| felix_ | oh, that's a good idea. thx :) | 14:57 |
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