Thursday, 2018-08-09

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se6astianhi felix_ how is the hardware review status ?06:51
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felix_uh, haven't heard anything from him yet :/14:30
se6astianwell can you check in with him14:31
felix_i'll try to reach him later14:33
se6astiangreat14:34
felix_just woke up; had an intercontinental flight yesterday that was planned to happen on the day before, but the international terminals of frankfurt airport got locked down that day14:37
felix_i brought the apertus flyers and stickers i still had with me to put them in the sticker box at defcon :)14:38
se6astiangreat14:38
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felix_rohit has a look at the design and liked it :)17:03
felix_i\ll have another look and go through the design checklist again17:04
felix_17:17 < rohitksingh> felix_: Hi! finally got around to taking a look at your axiom sdi design. From my point-of-view (FPGA and MGT section), it is quite great. I see you have gone with DC coupling of GTP tx lines from FPGA to output17:04
felix_                     driver.17:04
felix_17:17 < rohitksingh> felix_: I don't have much to add to that design, it is already quite beautifully designed and documented! good work!17:04
se6astiangreat17:04
felix_yep. found it quite amusing that he just wrote me when i wanted to poke him again :)17:31
felix_i\ll update the footprint of the capacitor on the sdi connector to the kicad 5 version; that should have slightly better rf properties17:34
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felix_somehow i used the old footprints in the design, but i'll only change it in the places where it's possibly performance-relevant17:51
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*** se6astian is now known as se6astian|away21:43
felix_i pushed a new version with the new capacitor footprints in the critical sdi paths23:43

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