Friday, 2018-06-29

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felix_Bertl_zZ: ist es eigentlich beabsichtigt, dass der vccio-pin vom pcie-style connector im gegensatz zu den anderen versorgungsspannungspins nicht gekuerzt ist?13:57
felix_oh, that wasn't english. i asked why the vccio pin isn't as short as the other vcc pins13:58
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Bertlthe fingers on the PCIe connector follow the 'usual' PCIe design for hotplug14:02
BertlVCCIO is normally not powered during hotplug, so it's not a problem14:02
felix_ah, ok; with vccio not being powered that makes sense14:03
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felix_now with the final outline and better edge connectors i.imgur.com/brCLYae.png17:11
felix_the board is now 62.6mm long17:12
felix_definitely won't get smaller; maybe 4mm bigger, but i'd say that everything will fit17:12
felix_(that size is including the pcie-style connector)17:15
Kjetilbtw. There is some layout recommendations for the xtal in the SI5342 reference manual (chap. 12)17:22
felix_yep, have seen that, but haven't created the xtal package yet17:23
felix_only thing i really dislike about working on pcb layouts is having to create the footprints i want to use, but usually i have to create footprints for stuff, because the not completely trivial ones from the library are often rather bad17:28
KjetilLast time I was playing around with a layout I got the footprints from digikey. (Ultralibrarian) To bad some of the symbols sucked17:29
BertlUltralibrarian is a plague17:32
Bertlmost of the (now) metric footprints end up aligned to an imperial grid17:32
Bertlwhich causes a lot of fun when routing them later ...17:33
Kjetilugh17:34
felix_the fpga symbols of the fpga could also be improved a bit (split into single io banks and not 2 io banks per symbol), but those were ok-ish; the footprints however weren't. i mean it's a really bad idea to have a qfn with non-segmented ground pad that is about 5x5mm big17:34
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felix_i.imgur.com/YrVnjTH.png enough for today :)22:44
Bertlnice22:46
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