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| *** RexOrCine is now known as RexOrCine|away | 01:51 | |
| *** se6astian|away is now known as se6astian | 07:16 | |
| *** Bertl_oO is now known as Bertl | 10:08 | |
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| *** RexOrCine|away is now known as RexOrCine | 17:53 | |
| felix_ | the power sequencing for the gtp voltage rails on the te0714 seems to be against xilinx' recommendation o_O | 18:40 |
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| *** se6astian|away is now known as se6astian | 19:18 | |
| *** se6astian is now known as se6astian|away | 21:35 | |
| felix_ | uh oh, it seems that oshpark doesn't support plugged vias | 21:51 |
| Bertl | that's why you do dog-bone breakouts | 21:54 |
| felix_ | the problem isn't the bga, but the capacitors on the other side | 21:55 |
| Bertl | place them around and in the middle channels | 21:56 |
| felix_ | hm, then i'll have to move the 4u7 capacitors somewhere else | 21:58 |
| felix_ | usually i place the 470n capacitors near the power supply vias and the 4u7 ones in the middle channels | 21:59 |
| Bertl | I presume you are using 0201 for the 470n | 21:59 |
| Bertl | btw, 470n? | 22:00 |
| felix_ | so should i try to squeeze as many capacitors near the fpgas power vias, put the rest somewhere near the fpga and hope that it works? doesn't sound too good to me tbh :/ | 22:00 |
| felix_ | yep, the 470n are in 0201 package | 22:00 |
| Bertl | so they should fit between the vias then, no? | 22:00 |
| felix_ | 470n is the xilinx recommendation | 22:00 |
| Kjetil | you should prioritize the GTP decoupling. The FPGA core is somewhat less senstive | 22:02 |
| Kjetil | But since the GTPs are at the chip edge that should'nt be to hard | 22:02 |
| Bertl | also you probably have a lot of 'unused' I/Os | 22:03 |
| Bertl | those banks can go with fewer capacitors | 22:03 |
| felix_ | oh, wait, when i move the capacitor a bit to the vias it is connected to, the drc passed | 22:03 |
| felix_ | the io banks aren't the problem; but i have quite some congestion in the middle and the gtp area | 22:03 |
| felix_ | the tricky part on the gtps is the routing of the gtp clock | 22:04 |
| felix_ | i hope that the soler paste won't flow into the vias, but i think this should work out; might cause some yield problems though with the soldering of the capacitors | 22:06 |
| Bertl | you can still cap the vias | 22:06 |
| felix_ | yeah, that might do the trick here. not sure how to do that in kicad yet, but i'll find out ;) | 22:09 |
| felix_ | meh, the solder mask opening from the capacitor opens about a third of the solder mask over the via | 22:15 |
| Bertl | for sure that can be adjusted | 22:25 |
| felix_ | does oshpark manage to get the layers well aligned nowadays? | 22:34 |
| felix_ | i've had problems with only small opening in the solder mask and not too great alignment of the solder mask layer | 22:36 |
| felix_ | ah, with the right value for the solder mask expansion it looks much better. i guess i should go home and get some sleep... | 22:55 |
| Bertl | have a good night then! | 23:13 |
| *** Bertl is now known as Bertl_zZ | 23:48 | |
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