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| se6astian | hi felix_ | 12:03 |
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| se6astian | how did the 3 day PCB phase go so far? | 12:03 |
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| felix_ | i have verified all already existing symbols i use, made most of the symbols that don't already exist (haven't really looked into how to do the clocking of the gtp yet), have the schematics maybe half-finished and looked more into the routability on the board | 12:57 |
| felix_ | routing congestion under the fpga is a bit of a problem, but so far it seems doable with some compromises | 12:58 |
| felix_ | the routing of the rather critical signals is no problem though | 12:58 |
| felix_ | on 6 layers the design would be much easier to do, but so far i'd say that it still is feasible with only 4 layers | 13:00 |
| felix_ | oh and this week i'll have more time to work on the project than i thought i'd have :) not full days, but still contigous blocks of maybe 4-5h | 13:01 |
| RexOrCine | Excellence. | 13:02 |
| felix_ | yesterday and today also weren't/isn't full days, but still finally got some good progress | 13:03 |
| felix_ | but yeah, i want to have this done before the 17.5., since i'll be in india for about two weeks from that day on | 13:04 |
| RexOrCine | Absolute completion? ie. the whole project? | 13:05 |
| felix_ | no | 13:05 |
| RexOrCine | Ah. | 13:05 |
| RexOrCine | This stage. | 13:05 |
| felix_ | "only" the design of the first prototype of the axiom-photonsdi-hw | 13:05 |
| felix_ | so when i'm away the board can be manufactured and maybe even already assembled | 13:06 |
| se6astian | sounds good | 13:08 |
| felix_ | the two bigger things that i have to solve unti then is the clocking of the gtps and to figure out how to route all the signals on the board in a way that the signal integrity of all signals won't be too bad | 13:09 |
| felix_ | can someone of you review some stuff this week or should i try to find someone else to do that? | 13:12 |
| Bertl_oO | what kind of review do you have in mind? | 13:14 |
| felix_ | first some review of schematic symbols and their mapping to the footprints, when i've finished the schematics a review of that and when i've finished the layout a review of the layout | 13:16 |
| felix_ | i always like to have someone elso to look a the finished design to catch some bugs i didn't see | 13:17 |
| felix_ | oh, in case you haven't already seen this: https://docs.google.com/document/d/1YRnNG3D8_12onXnyjq7ZIn70ye9aCjsMQ0Uf0hwOgzQ/edit i find it quite useful | 13:18 |
| tpb | Title: PCB signoff checklist - Google Docs (at docs.google.com) | 13:18 |
| Bertl_oO | nice, yeah I guess se6astian can do footprint checks, I'll do schematic and layout checks but if you find somebody else to do them as well, then even better | 13:20 |
| felix_ | sounds good | 13:20 |
| felix_ | oh and when the sdi board is finished, it's also probably not too difficult to make a hdmi variant from it; the fpga has enought gpts to drive a hdmi output. the routing will get a bit annoying though since only 2 gtp pairs are easily routeable; the other two have to be routed to the fpga on the bottom layer and the layer next to the bottom layer is quite fragmented | 13:48 |
| felix_ | *gtps | 13:49 |
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