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| elijaxapps | Hi. I was a hobbyist planning to become the great one first to clone an x86 CPU and I found this https://opencores.org/projects/ao486 . Great job ruining my dream :P Mine design is in Logisim circuit simulator, the fun thing is that you can run simulations up to 4Khz, fast enough for a DOS system (AFAIR, my 8088 of the 80's had that horses, and ran DR-DOS). I was planning to make a video of how I load a DOS ramdisk (Logisim li | 19:35 |
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| elijaxapps | ), invoke QBasic and write a Hello World program :D Like inception but using logic. | 19:35 |
| tpb | Title: Overview :: ao486 :: OpenCores (at opencores.org) | 19:35 |
| elijaxapps | Oh man I can't wait to contact Aleksander Osman xD Does he stops here sometimes? | 19:40 |
| ZipCPU | elijaxapps: Sadly, this channel has fallen into disuse, much as the OpenCores forums has | 20:43 |
| ZipCPU | There are those who would like to resurrect the name of OpenCores again, but you'll probably find a new group of people doing so if at all | 20:43 |
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| elijaxapps | Well, the sources are still available. Now I am trying to use logisim-evolution to import Verilog files into an schematic. At first glance in a Google search seems doable. | 21:41 |
| elijaxapps | Also, there are a Cyrix 586 clone, and a 80286 clone, amongst some other x86. Still sound promiseful for me. | 21:43 |
| elijaxapps | Both fits my needs. In the worst scenario I only have to change Logisim for a Verilog tool (for the video part, the remaining is mine design is pretty small compared to that ones). | 21:46 |
| elijaxapps | I.e it's alu is an additor + a xor gate if I recall correctly, but have 32 bits of addressable memory. And runs at 64Hz ... xD (that with the old Logisim; I was not aware it was deprecated when I started, now importing breaks things ... ) | 21:49 |
| ZipCPU | Have you seen any of my blogs on the topic? | 21:49 |
| ZipCPU | For example, I've posted regarding a VGA simulator you can use with Verilator | 21:49 |
| elijaxapps | Good, Verilator does have GUI? The fun thing about verilog was being able to see the computer working. | 21:51 |
| elijaxapps | s/verilog/logisim | 21:52 |
| ZipCPU | No. Verilator doesn't have a GUI. | 21:52 |
| ZipCPU | The Sim integrates into the local GTK++ libraries | 21:52 |
| elijaxapps | or some circuit representation at minimum? | 21:52 |
| ZipCPU | Verilator is a Verilog to C++ converter | 21:53 |
| ZipCPU | Check out http://zipcpu.com/tutorial/ for more information on both Verilog, Verilator-based simulation, and formal methods | 21:53 |
| tpb | Title: Verilog, Formal Verification and Verilator Beginner's Tutorial (at zipcpu.com) | 21:53 |
| elijaxapps | yeah I was already reading :) | 21:55 |
| elijaxapps | You know, an hour ago I was asking for a mentor ins ##asm to rewrite my microcode with existing Schematic. Is fun, yeah, you could do things, etc but it is nothing compared to those Verilogs projects you have hosted... And just read about what you say FPGA Hell. xD | 21:58 |
| elijaxapps | I will make a candidate release just to share. It have taught a lot to me and could serve to others I think. Even my own design is based in Ben Eater's 8 bit CPU which is also free. | 22:01 |
| elijaxapps | Will read your blog and hang here for some time :) | 22:02 |
| ZipCPU | ;) | 22:02 |
| elijaxapps | Read preface and chapter 1. I'll try to set up the environment tomorrow. Thanks a lot. I'll ask you about that VGA simulator you said you have in the future. | 22:55 |
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