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| IPittUPitt | Has anyone had experience with litedram overriding timing parameters? I'm trying to modify the refresh interval for my DDR3 module but it doesn't appear to be propagating to the HDL design. | 19:37 |
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| IPittUPitt | For example, when changing tREFI from 64e6/8192 to 64e6 I would expect errors due to charge loss | 19:40 |
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