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| riktw | Heya. I have a, hopefully, simple question. I would like to divide the clock by 2 with a simple flip flop or such, and not a PLL. Is this easy to add/implement? For example, the digitlent_arty uses the PLL to generate a 25Mhz clock from the 100Mhz for the Ethernet PHY. Would this also be doable with a simple flip flop approach in Litex? | 20:23 |
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| nats` | it's always doable to divide a clock with flip flop, but that's also always a bad idea :) | 21:09 |
| nats` | a lot of problem will appears if you use this new 'signal' to drive logic | 21:09 |
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