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| promach3 | Do anyone see anything wrong with the DDR3 initialization sequence shown in https://github.com/promach/DDR/blob/main/ddr3_memory_controller.v#L789-L987 ? | 05:00 |
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| zyp | _florent_, I've got a patch series for litespi coming up; some feature additions, some performance fixes and some unrelated minor fixes -- would you like it all as one big PR, or should I submit the feature stuff and the performance stuff separately? | 10:28 |
| zyp | related tickets are #46 and #45 respectively | 10:29 |
| _florent_ | promach3: I would recommend doing a simulation of your controller with a DDR3 memory model from Micron, this can be very useful to debug your initialization issue | 10:49 |
| _florent_ | Here is the code generating the DDR3 initialization sequence in LiteDRAM is this can be useful: https://github.com/enjoy-digital/litedram/blob/master/litedram/init.py#L119-L226 | 10:51 |
| zyp | _florent_, side note: is there a mechanism to hook stuff into the bios firmware from outside the litex repo? it'd be nice to have stuff like liblitespi in the litespi repo instead, so it's easier to keep the software and gateware in sync | 10:53 |
| _florent_ | zyp: Thanks, I'm not well familiar yet with the LiteSPI code, so if that's too complicated for you, small PRs for each fix/features will be easier to review/merge | 10:54 |
| zyp | yeah, I think I just decided to submit a PR for the feature stuff now, since that's mostly done, and then I'll do another later for the performance stuff | 10:55 |
| _florent_ | zyp: for now no, but I also want to go in this direct in the long term: https://github.com/enjoy-digital/litex/issues/757 | 10:55 |
| _florent_ | sorry it can sometimes takes a bit of time for things to move :) | 10:56 |
| zyp | I think you were pretty quick about merging the PR I submitted yesterday :) | 10:56 |
| zyp | do you have any thoughts about how the software libs should hook into the bios? I'd be happy to have a look at that when I can find time | 10:58 |
| _florent_ | Sorry I also still need to have a closer look at it, if you want have a quick look and have idea, feel free to discuss this in #757 | 10:59 |
| _florent_ | The idea is also to move the gateware integration methods to the core itself | 11:00 |
| _florent_ | sorry I have to go | 11:01 |
| zyp | that sounds reasonable, means the main repo doesn't need to know about all the subprojects | 11:01 |
| zyp | np | 11:01 |
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| _florent_ | yes, this way LiteX would just do the plumbing :) | 11:05 |
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| Wolf` | Anyone playing with Xilinx Virtex Ultrascale HBM parts? | 11:09 |
| promach3 | <_florent_ "promach: I would recommend doing"> _florent_: however Micron simulation model does not support DLL off mode yet | 11:11 |
| promach3 | <_florent_ "Here is the code generating the "> _florent_: How do I exactly use this python script ? why you specifically highlight those few code segments ? | 11:12 |
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| promach3 | I ran `python init.py` , but no output files are created. No terminal output as well | 11:28 |
| promach3 | or should I use https://github.com/enjoy-digital/litedram#-tests ? | 11:30 |
| promach3 | _florent_: | 11:30 |
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| shoragan | is using litex_boards as an installed python module support? | 11:41 |
| shoragan | i mean something like python3 -m litex_boards.targets.lambdaconcept_ecpix5 --build | 11:41 |
| shoragan | it seems to work, but i see "RuntimeWarning: 'litex_boards.targets.lambdaconcept_ecpix5' found in sys.modules after import of package 'litex_boards.targets', but prior to execution of 'litex_boards.targets.lambdaconcept_ecpix5'; this may result in unpredictable behaviour" | 11:42 |
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| promach3 | _florent_: I am not sure how to generate DDR3 initialization sequence using https://github.com/enjoy-digital/litedram/blob/master/litedram/init.py#L119-L226 | 13:51 |
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| mithro | zyp: Thanks for your interest in litespi! | 14:12 |
| mithro | zyp: I'm going to try and get someone to look at your suggestions | 14:12 |
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| nickoe | promach3: _florent_ .. a bit related to dram sim.. do you know why I hw and sim appears to differe like this? https://github.com/enjoy-digital/litedram/issues/251 | 19:06 |
| nickoe | OMG, I was wondering why a csr storage value was 3 when I set the reset to something else... it turned out that I very early on in the software app set it to 3... | 19:16 |
| nickoe | Sooo that is good, back to stuff working as intended and I understand _why_, at least more or less. | 19:17 |
| nickoe | :D | 19:17 |
| zyp | that's the best combination | 19:18 |
| nickoe | zyp: I guess it is ok to take a couple of days break from it once in a while :D | 19:28 |
| _florent_ | promach3: I was pointing to LiteDRAM DDR3 initialization just to give you a reference for the initialization sequence | 19:31 |
| _florent_ | you don't really need to generate it, but you can just see it as pseudo code to compare with your initialization sequence | 19:32 |
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| Wolf` | unrelated: The HBM2 init sequence is DAMN complex. | 21:18 |
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