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DurandA | Hi. I am looking for some help to use CSRs (not CSRStatus or CSRStorage). Specifically, I try to do a self-resetting CSR. Currently, the CPU/remote has to send a pulse to an "enable" CSRStorage. | 04:32 |
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DurandA | I didn't find something like that in the codebase. Thanks for your ideas. | 04:34 |
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nickoe | _florent_ Did you see my "question" in https://github.com/enjoy-digital/litedram/issues/251#issuecomment-835897878 ? | 16:53 |
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nickoe | zyp: Mm, is this the correct to create a nullsink with the stream endpoint? https://pastebin.com/raw/5jYVhtjc | 20:04 |
zyp | yes | 20:05 |
zyp | and a nullsource would equivalently have valid always high | 20:05 |
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nickoe | mm, but then I wonder why this does not appear to work :S | 20:12 |
nickoe | https://i.snipboard.io/Nexv3K.jpg | 20:13 |
nickoe | zyp: With this code https://pastebin.com/raw/p5UTedKw | 20:13 |
nickoe | so I just connected the dma to the nullsink | 20:14 |
nickoe | but why does the dma source ready signal go low? | 20:14 |
nickoe | oh, I also have the cdc in between, but it should still not do that all the time. | 20:16 |
zyp | self.comb += dma.source.connect(cdc.sink) | 20:16 |
zyp | self.comb += cdc.sink.connect(nullsink.sink) | 20:16 |
zyp | that should be cdc.source | 20:16 |
nickoe | Ohh, nice. I must be blind today. | 20:17 |
zyp | also, you might want to use a Pipeline() to hook this up | 20:17 |
zyp | Pipeline(dma, cdc, nullsink) is a bit more readable than what you've got now :) | 20:17 |
nickoe | I can't finde that, is that a litex thing or migen? | 20:18 |
zyp | it's in litex.soc.interconnect.stream | 20:18 |
zyp | like all other stream constructs | 20:18 |
nickoe | ok, I see it | 20:18 |
nickoe | not sure what was wrong with my search thing | 20:19 |
zyp | I suggest you have a read through that module, it's got a bunch of convenient building blocks | 20:19 |
nickoe | yeah, well, but not a hell lot of documentaiton :S So it is hard to find what "I didn't know I needed" when I don't know what they do. :D | 20:20 |
nickoe | but that do look more readable indeed. | 20:20 |
nickoe | But at least I am sorta getting the gang of understanding the internals with a glance | 20:26 |
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nickoe | zyp: Why does it appear that this storage is equal to 3? no matter what reset value I set it to? | 20:36 |
nickoe | https://pastebin.com/raw/ThntnD5t | 20:36 |
zyp | is it not hooked up to anything? | 20:37 |
nickoe | like this https://github.com/nickoe/litex-boards/blob/mars_ax3_sim/litex_boards/targets/mars_ax3_custom.py#L295 | 20:38 |
nickoe | I just tried to disconnect it from the module.. | 20:38 |
nickoe | to see if that changes maters | 20:38 |
nickoe | there is also this? https://github.com/nickoe/litex-boards/blob/mars_ax3_sim/litex_boards/targets/mars_ax3_custom.py#L323 | 20:39 |
nickoe | If(self.upsample_num.re, | 20:39 |
nickoe | Even if I remove any uses of it it is till just 3 | 20:42 |
nickoe | even with https://pastebin.com/raw/6kkB0H7d | 20:43 |
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