*** tpb has joined #litex | 00:00 | |
*** Degi_ has joined #litex | 00:17 | |
*** Degi has quit IRC | 00:19 | |
*** Degi_ is now known as Degi | 00:19 | |
*** peeps[zen] has joined #litex | 00:25 | |
*** peepsalot has quit IRC | 00:26 | |
*** pftbest has quit IRC | 00:28 | |
*** FFY00_ has quit IRC | 02:50 | |
*** cjearls has joined #litex | 04:30 | |
*** cjearls has quit IRC | 04:31 | |
*** peeps[zen] is now known as peepsalot | 04:33 | |
*** Bertl_oO is now known as Bertl_zZ | 05:33 | |
*** pftbest has joined #litex | 07:21 | |
*** kgugala has quit IRC | 08:03 | |
*** kgugala has joined #litex | 08:04 | |
*** kgugala_ has joined #litex | 08:07 | |
*** kgugala has quit IRC | 08:07 | |
*** kgugala has joined #litex | 08:58 | |
*** kgugala_ has quit IRC | 08:58 | |
nickoe | Melkhior: Maybe it is because they are just wires and not a register? | 09:21 |
---|---|---|
*** cjearls has joined #litex | 11:50 | |
*** TMM has quit IRC | 11:55 | |
*** TMM has joined #litex | 11:55 | |
nickoe | Why does it appear as if the date I get from the LiteDRAMDMAReader when using native port width is garbarage? It works when I set data_widt to 8? | 12:13 |
*** Bertl_zZ is now known as Bertl | 13:13 | |
*** pftbest has quit IRC | 13:40 | |
*** pftbest has joined #litex | 13:41 | |
*** pftbest has quit IRC | 14:02 | |
*** pftbest has joined #litex | 14:06 | |
*** DrWhax has joined #litex | 15:12 | |
*** CarlFK1 has joined #litex | 15:48 | |
*** CarlFK1 has quit IRC | 15:53 | |
*** pftbest has quit IRC | 15:57 | |
*** pftbest has joined #litex | 16:04 | |
*** Bertl is now known as Bertl_oO | 17:25 | |
*** pftbest has quit IRC | 17:37 | |
*** pftbest has joined #litex | 17:40 | |
*** pftbest has quit IRC | 17:50 | |
*** pftbest has joined #litex | 17:52 | |
*** FFY00_ has joined #litex | 18:04 | |
*** TMM has quit IRC | 20:55 | |
*** TMM has joined #litex | 20:55 | |
*** kgugala_ has joined #litex | 21:14 | |
*** kgugala has quit IRC | 21:16 | |
nickoe | Ok, I finally made it work, it appears that if I used more than 8 as data width, I need to hold the address for more clock cycles... | 21:18 |
zyp | were you not looking at the ready signal? | 21:42 |
*** cjearls has quit IRC | 21:55 | |
nickoe | zyp: mmm, not when changing the address | 21:59 |
nickoe | zyp: So now I do it like this, https://github.com/nickoe/litex-boards/blob/7ca4099b4b050ea2addecf6e2610a57cf4c757fe/litex_boards/targets/mars_ax3_sim_litex.py#L253-L256 | 22:00 |
nickoe | I am not sure if there is a better way to do it than to assume it will take two cycles :S | 22:01 |
*** rj has quit IRC | 22:07 | |
*** mikeK_de1soc has joined #litex | 22:29 | |
zyp | okay, I'm not familiar enough with it to tell | 22:47 |
*** mntmn has quit IRC | 23:01 | |
*** mntmn has joined #litex | 23:03 | |
*** lf_ has quit IRC | 23:16 | |
*** lf has joined #litex | 23:16 |
Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!