Sunday, 2021-05-02

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nickoeMelkhior: Maybe it is because they are just wires and not a register?09:21
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nickoeWhy does it appear as if the date I get from the LiteDRAMDMAReader when using native port width is garbarage? It works when I set data_widt to 8?12:13
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nickoeOk, I finally made it work, it appears that if I used more than 8 as data width, I need to hold the address for more clock cycles...21:18
zypwere you not looking at the ready signal?21:42
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nickoezyp: mmm, not when changing the address21:59
nickoezyp: So now I do it like this, https://github.com/nickoe/litex-boards/blob/7ca4099b4b050ea2addecf6e2610a57cf4c757fe/litex_boards/targets/mars_ax3_sim_litex.py#L253-L25622:00
nickoeI am not sure if there is a better way to do it than to assume it will take two cycles :S22:01
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zypokay, I'm not familiar enough with it to tell22:47
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