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| jhu | _florent_ Thanks I will ask them! | 17:07 |
|---|---|---|
| nickoe | Is there somewhere with a good overview of the differences between "normal" AXI, AXI Lite and AXI Stream? | 18:23 |
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| nickoe | mmm, I tried to follow the guide to include a verilog module | 19:00 |
| nickoe | But I a wondering why the "output pin" dac_cw is way out of phase? https://i.snipboard.io/DOG20X.jpg | 19:03 |
| nickoe | signal wire defined as Subsignal("cw", Pins("L3"), IOStandard("LVCMOS33")), | 19:04 |
| nickoe | I would expect led and dac_cw to be in phase. | 19:05 |
| _florent_ | nickoe: GTKwave allow you to shift signals, you probably did it unintentionally, you can just remove the signals and add them again | 19:22 |
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| nickoe | ohh, puhh, good! I thought something was annoying and inexplicably out of wack! | 19:25 |
| nickoe | Can I do LiteDRAMDMAReader -> AXIStreamInterface -> dac_plat? ? | 19:25 |
| nickoe | or I have a verilog module that is supposed to take some axi interface and do the correct thing on the "dac_plat" output pins, https://dpaste.com/BXWEKN6RZ.txt | 19:27 |
| nickoe | (that someone else wrote on my "team") | 19:27 |
| nickoe | for that verilog file wiht "#(parameter IN_DATA_WIDTH=20)" can I specify that in the Instance()? | 19:31 |
| nickoe | or is that p_? | 19:36 |
| nickoe | prefix | 19:41 |
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