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| _florent_ | tcal: Thanks, I need to think a bit about the CFU integration. I also need to do similar work on VexRiscv-SMP to expose some of the parameters to targets (cpu-count, aes, fpu, etc...) so will think about the CFU for VexRiscv and others RISC-V CPU while doing this. | 06:08 |
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| _florent_ | tcal: Would you mind opening an issue for this in LiteX? | 06:08 |
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| Melkhior | @_florent_ I have an example at home for some VexRiscv parameters; i added a '--extensions' to litex/soc/cores/cpu/vexriscv_smp/core.py (which I passs from linux-on-litex-vexriscv/make.py), so I can do : | 07:53 |
| Melkhior | --extensions I,M,A,C,F,D,B,Zbr,Zbt,Zkn,Zks | 07:53 |
| Melkhior | (I,M,A are redundant of course but make things more readable for me) | 07:53 |
| Melkhior | F & D enables the FPU | 07:53 |
| Melkhior | C enable compressed instructions | 07:53 |
| Melkhior | B and latest enables my custom plugins; Zkn for instance could enable AesPlugin (I have a patch to make AesPlugin Zk-compliant, but it will have to be updated as Zk is going to revert some opcode space optimization) | 07:53 |
| Melkhior | code on the 'reciving' end in VexRiscv is visible on https://github.com/rdolbeau/VexRiscv/tree/three_operands, e.g. https://github.com/rdolbeau/VexRiscv/blob/three_operands/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala | 07:53 |
| Melkhior | s/reciving/receiving/ | 07:53 |
| Melkhior | I've also added the extensions in MISA and the arch string so that it appears in e.g. /proc/cpuinfo | 08:03 |
| geertu | Melkhior: we already have riscv,isa under /proc/device-tree/.../cpu@0/ ? | 08:07 |
| Melkhior | @geertu yes: | 08:09 |
| Melkhior | root@buildroot:~47 cat /proc/device-tree/cpus/cpu\@3/riscv\,isa ; echo | 08:09 |
| Melkhior | rv32imafdcb | 08:09 |
| Melkhior | @geertu question: in riscv,isa, should non-std extension appears and how ? In MISA you add 'x' if there's any, but for riscv,isa should we a) ignore them b) add an 'x' c) add the canonical Z order ? (rv32imafdcbZbr_Zbt_Zkn_Zks) | 08:53 |
| Melkhior | also Z is for 'somewhat standard' so not even sure if it's 'x'... | 08:54 |
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| geertu | Melkhior: see Documentation/devicetree/bindings/riscv/cpus.yaml | 14:05 |
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| Melkhior | @geertu thanks, could have guessed;-) , so this is the full specification apparently | 16:03 |
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| tcal | _florent_: thanks, I've created issue #883. | 16:43 |
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| nickoe | bruh, I better start to play with litex again ... soon | 20:09 |
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