Saturday, 2021-04-10

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thorns514if I have a uart that I want to use to serialboot some firmware, and then reuse in lxserver to connect to litescope_cli, is this possible ?00:54
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thorns514if I have a USB debug bridge working with a valenty DummyUsb core in my soc, verified with wishbone-tool, should I expect this also to work with litescope using lxserver?16:21
zypyes16:23
dkozelIs there a way to load a new bitstream to the CLE-215 over LitePCIe _florent_ ?16:25
zypisn't that what the ICAP module is for?16:27
thorns514ok thanks, I need to figure out why it reports no regs then ..16:28
dkozelzyp: I'll go take a look16:28
dkozelFirst glance is that should allow partial reconfiguration which is essentially the goal. Most literature is about reconfiguring from an internal softcore, but presuably the interface can be wired to an external facing bus like PCIe16:32
zypIIRC the litex module just exposes it as a couple of registers on the CSR bus16:52
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_florent_dkozel: with the Acorn, adding S7SPIFlash as a flash submodule will allow you to update the bistream in SPI Flash with the LitePCIe utilities17:04
_florent_https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/spi_flash.py#L35717:05
_florent_Adding ICAP as icap submodule will allow you to reload the bistream with the LitePCIe utilities17:05
_florent_https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/icap.py#L1717:06
_florent_similar to this:17:06
_florent_https://www.irccloud.com/pastebin/DLsV86sa/17:07
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)17:07
zyp_florent_, question: what does generic_platform.Inverted do?17:08
thorns514does the litescope cli/RemoteClient need the soc csr.csv (with all the CSR regs and memory map etc), in addition to the analyzer CSV with the tapped wires?  it's complaining that the remote has no "regs", and it works if I rename the file that I saved my soc --csr-csv to as csr.csv (which the RemoteClient seems to default to) ...17:10
zypthe reason I'm asking is because I'm about to put some more work into my luna wrapper, and I want it to automatically adapt to the phy used on the platform17:10
zypulpi phys can have reset being either active high or active low, and the clock can either be an input or an output17:10
zypfor the clock I'm planning to distinguish on whether the pads have a clk or clk_o signal, and I'm wondering if I should do similar with reset, or if this is what the Inverted annotation is meant for17:12
_florent_zyp: Inverted was introduced as a quick workaround for some NeTV2 use cases, I'm not sure we should expand it for now (at least I would like to revisit it first)17:39
zypI see, that explains why I didn't see much use of it when I grepped around17:40
_florent_thorns514: LiteScope indeed also needs the csr.csv to get the register mapping (analyzer.csv only provides the mapping of the analyzer signals)17:40
zypin that case I think I'll call it rst_n if it's active low17:40
thorns514_florent_: thanks, yeah I am prepping a PR to add a better warning if your CSR is not csr.csv.  But I'm still trying to get a good trace first.  I'm triggering on the CYC of my bus slave for instance, but the trace that pops out (immediately) has no CYC raise in it17:42
zyp_florent_, you've got two PRs from me in litex-boards now: https://github.com/litex-hub/litex-boards/pull/199 https://github.com/litex-hub/litex-boards/pull/201 :)17:46
thorns514I keep getting traces that are definitely not random, but not at all related to my triggers17:54
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thorns514maybe I'll try tapping the cpu wires like the example instead of my verilog instance bus wires17:57
thorns514yeah I dunno, I can't find any rhyme or reason to these triggers, mysterious18:13
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thorns514aha well I got my module working at least, even if I never figured out the litescope triggering problem19:11
thorns514never saw a CYC high at all...19:11
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_florent_zyp: thanks for the PRs, I'll review them very soon19:46
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