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| _florent_ | sajattack[m]: With PCIe, on 7-Series I generally used the multiboot feature that allows having a golden bitstream + operational bitstream in SPI Flash | 05:21 |
|---|---|---|
| sajattack[m] | how does that work? | 05:21 |
| _florent_ | At startup, the FPGA jumps to the operational bitstream and fall back to the golden bitstream if operational bitstream is corrupted | 05:21 |
| sajattack[m] | can I do that with openocd? | 05:22 |
| _florent_ | This way you can safetly update the operational bitstream in SPI Flash and knows it will able to recover even if flashing is not successful | 05:23 |
| _florent_ | With LitePCIe, LitePCIe already provides the MMAP interface (for AXI-Lite/Wishbone/CSR registers) and the bistream just need to have a SPI core connected to the SPI Flash | 05:24 |
| _florent_ | you can then just do updates over PCIe | 05:24 |
| sajattack[m] | ok cool | 05:24 |
| _florent_ | So you just need to configure a first time over JTAG, after that you no longer need it | 05:25 |
| sajattack[m] | but I need to write something to send the update to the spi flash? or it's already written? | 05:26 |
| _florent_ | I'm planning to share examples for that for the Acorn soon | 05:26 |
| sajattack[m] | sweet | 05:26 |
| _florent_ | it's already there: https://github.com/enjoy-digital/litepcie/blob/master/litepcie/software/user/litepcie_util.c#L84-L252 | 05:27 |
| sajattack[m] | that's awesome | 05:28 |
| sajattack[m] | is rescan sufficient or needs a full reboot to work? | 05:28 |
| sajattack[m] | like this https://github.com/enjoy-digital/litepcie/issues/36 | 05:30 |
| _florent_ | but I want to rework it a bit, the current implementation use a hardware SPI core, but for another design I just did the reflashing over bitbanging and it was in fact more flexible and faster, so I want to switch the LitePCIe example SPI Flash update to bitbanging (which would by the way also allow having the SPI Flash mmaped in the SoC for reads). | 05:30 |
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| _florent_ | yes this should be enough, you just need to also reload the bitstream first with https://github.com/enjoy-digital/litepcie/blob/master/litepcie/software/user/litepcie_util.c#L233-L252 | 05:31 |
| sajattack[m] | yes | 05:31 |
| sajattack[m] | do I just define CSR_FLASH_BASE in CFLAGS to 1 or is it something that needs to be set up a bit more than that? | 05:33 |
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| _florent_ | In fact with the current code you just need to have this in your SoC: | 05:34 |
| _florent_ | https://www.irccloud.com/pastebin/4ioxldCH/ | 05:34 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 05:34 |
| sajattack[m] | ok | 05:35 |
| _florent_ | with the flash pins defined similar to this: | 05:35 |
| _florent_ | https://www.irccloud.com/pastebin/pXclz7TB/ | 05:35 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 05:35 |
| _florent_ | This will create the defines and will enable Flashing in the LitePCIe driver | 05:36 |
| sajattack[m] | cool | 05:36 |
| sajattack[m] | thanks! | 05:36 |
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| * sajattack[m] < https://matrix.org/_matrix/media/r0/download/matrix.org/mfuYEigcoSHfOaghcNVWqDOB/message.txt > | 08:19 | |
| sajattack[m] | looks like `-f` | 08:21 |
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| Melkhior | @somlo Great tutorial on your work with Linux-on-Litex-Rocket at the RISC-V week https://open-src-soc.org/2021-03/ ! | 14:00 |
| Melkhior | And nice plug of #litex in the Q&A :-) | 14:00 |
| tpb | Title: 2nd RISC-V Week: 3rd RISC-V Meeting + OpenHW Day (at open-src-soc.org) | 14:00 |
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| somlo | Melkhior: thanks! | 19:53 |
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