Saturday, 2021-03-27

« Friday, 2021-03-26 Index Sunday, 2021-03-28 »
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_florent_leons: Initial boards support are generally not perfect/complete, so integrating your board even with DRAM not yet working would be perfectly fine (we would just avoid enabling DRAM or list the limitation). This is also a good way to work together on this or get help from other developers having the same board.08:08
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MelkhiorHello,13:47
MelkhiorGot myself a new board with an on-board Ethernet for Litex, but when configuring an IP under Linux I only get:13:47
Melkhiorliteeth f0004800.mac eth0: LITEETH_READER_READY timed out13:47
Melkhiorrepeated a few times.13:47
MelkhiorOnly trace I found of the error message is a year-old discussion...13:47
MelkhiorAny idea ?13:47
MelkhiorBoard is a Qmtech Wukong (cheap Artix 7 100k, comfortably fit 4 VExRiscv cores with all the bells and whistles :-) )13:47
MelkhiorRunning the "default" kernel for linux-on-litex-vexriscv:14:02
MelkhiorBR2_LINUX_KERNEL_CUSTOM_REPO_URL="git://github.com/litex-hub/linux.git"14:02
MelkhiorBR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="7d6b20bd1aa8276d92504fa540bd0a903ef43610"14:02
Melkhior(with only C/F/D added & NFS support)14:02
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mikeK_de1socHi Florent! I got the Video terminal to work on the DE1-SoC! How do I use the keyboard now? Or can I log in with the lxterm? I am not sure how to do this.. Thanks. MikeK14:12
MelkhiorAlso reconfigured the IP in the BIOS, but the interface doesn't ping and the server doesn't see any request when trying to netboot...14:21
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MelkhiorOK, so I fixed the platform/targets definition of the board (the hardwxare description says it's a GMII interface), now Linux doesn't complaint anymore ; the interface sends ARP request, but doesn't seen the answer and doesn't ping, guessing it never receives data...16:35
MelkhiorI have a 80 MHz system clock, maybe it's too slow for GbE ?16:36
_florent_mikeK_de1soc: Yes the Video Terminal is a recopy of the UART output, so you still can interact with the SoC with lxterm16:52
_florent_Melkhior: The best would be to get netboot behaving correctly first yes16:53
_florent_You can enable software debug traces in the BIOS with software_debug=True:16:54
_florent_https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L135516:54
_florent_This will display the TX/RX frames16:54
_florent_This will allow you to see the received RX frames and eventually understand the issue16:55
_florent_With GMII, all boards/PHYs are not configured the same regarding TX/RX Clk/Data delays16:56
_florent_So that's possible you'll have to adapt them:16:56
_florent_https://github.com/enjoy-digital/liteeth/blob/master/liteeth/phy/s7rgmii.py#L21016:56
_florent_tx_delay and rx_delay16:56
_florent_You can also try to play with MDIO from the BIOS to dump/modify the PHY registers16:57
Melkhior_florent_ not sure I understand... I don't even understand where the clocks for the ethernet comes from; there's a 125 MHz RX from the board, but I have no 125 MHz clock in my design to supply the GTX clock...16:59
Melkhiorso can I still run GbE ? But then for MII mode (fast ethernet I guess) I need a 25 MHz clock, I don't have that either17:00
Melkhiorso I'm a bit lost long before the delay stuff :-/17:01
Melkhiorlitex> mdio_dump 0 1617:02
MelkhiorMDIO dump @0x0:17:02
Melkhior0x00 0x114017:02
Melkhior0x01 0x796917:02
Melkhior0x02 0x001c17:02
Melkhior0x03 0xc91517:02
Melkhior0x04 0x05e117:02
Melkhior0x05 0xc5e117:02
Melkhior0x06 0x000f17:02
Melkhior0x07 0x200117:02
Melkhior0x08 0x600117:02
Melkhior0x09 0x020017:02
Melkhior0x0a 0x3c0017:02
Melkhior0x0b 0x000017:02
Melkhior0x0c 0x000017:02
Melkhior0x0d 0x000017:02
Melkhior0x0e 0x000017:02
Melkhior0x0f 0x300017:02
Melkhiorare those the CSR from "class LiteEthPHYMDIO" ?17:04
_florent_The TX clock will be generated from the RX clock17:04
_florent_https://github.com/enjoy-digital/liteeth/blob/master/liteeth/phy/s7rgmii.py#L142-L20417:05
MelkhiorOh, now it makes sense thank you :-)17:07
Melkhioralso a dumb question: is the "200MHz IDELAYE2 REFCLK" the clock that some Artix 7 board define as cd_idelay ?17:08
_florent_RGMII has specific IO timings:17:09
_florent_https://e2e.ti.com/resized-image/__size/1230x0/__key/communityserver-discussions-components-files/138/2352.2.png17:09
Melkhiorfor S7IDELAYCTRL17:09
_florent_But timings are not always handled the same way depending the boards/PHY, so we sometimes have to adjust them in the FPGA PHY17:10
_florent_yes cd_idelay is the reference for the S7IDELAYCTRL17:10
_florent_https://usercontent.irccloud-cdn.com/file/ATvSgrE5/image.png17:12
MelkhiorSo if my cd_idelay is defined as 2*sys_clk_freq it's not 200 MHz and it migh mess things up ? The board does that (so does mine), probably because the MMCM sometimes fails to generate all the clocks if they are unrelated in requency...17:13
_florent_You can see here that the delay can be adjusted: In the FPGA, through the Clk traces and also in the PHY17:13
_florent_yes you have to make sure that the S7IDELAYCTRL reference clock is 200MHz17:14
_florent_if you have difficulties generating all the clock with a single PLL, you can also use a specific PLL for the cd_idelay17:14
MelkhiorYes, I think I get that, I had to try to understand the principle to get the set_input_delay/set_output_delay right to interface with the SBus (all 82 parallel signals of it)17:14
MelkhiorOK, I can use more than one PLL ? good news17:15
Melkhiorrebuilding with the proper idelay clk & the software debug17:15
MelkhiorI will not find the trace information for this board, el-cheapo board from aliexpress17:16
Melkhior(but if everything works out-of-the-box I don't get to learn)17:16
Melkhiorthanks for the pointers I'll try to make sense of things17:17
_florent_yes you can use multiple PLLs (on a xc7a100t you have 6 CMTs (1 MMCM + 1 PLL))17:17
Melkhioralso, on this board, the micro-sd card (on a pmod thingy) works fine, and I was able to write a file from Linux ... my own board must have an issue :-(17:17
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MelkhiorOK, if I get the ethernet working I'll do a PR for it17:20
Melkhiorthanks again17:20
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Melkhior_florent_ update: with the fixed idelay clock, the system netboot just fine, but linux still won't ping or be pinged or do any tcp traffic. As far as I can tell, it does emit the ARP request but doesn't see the reply (the arp table is always 'incomplete' for all other systems)18:21
Melkhioranyway it's already progress :-)18:22
leonsMelkhior: I had that exact same issue yesterday!19:09
leonsThough after reading florent's statements, my solution is probably wrong and it's still flaky for me19:10
leonsI just tried adding `self.add_period_constraint(self.lookup_request("eth_clocks:tx", loose=True), 1e9/125e6)` (so adding the constraint for both RX and TX clocks)19:11
leonsIt works with my Desktop NIC, but my Ethernet switch doesn't like it. I suppose this is not accounting for the phase offset required19:11
leonsDisclaimer: I don't understand much of this, just trial and error on my side :)19:12
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