Thursday, 2021-03-25

« Wednesday, 2021-03-24 Index Friday, 2021-03-26 »
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* sajattack[m] < https://matrix.org/_matrix/media/r0/download/matrix.org/uoqEBMKVCJkimkcxdJDcGHbO/message.txt >00:42
sajattack[m]nevermind, got it00:45
sajattack[m]lol I typed lspci after flashing and my computer rebooted itself00:51
sajattack[m]attempting to load the kernel module also results in a kernel panic/reboot01:05
sajattack[m]unfortunately there's a gap in the journalctl log between the command to load the driver and the next boot01:14
sajattack[m]kernel 5.11.801:17
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sajattack[m]ok, got the `/dev/litepcie0` showing up now, but `litepcie_util info` locks up my computer for about 30 seconds, doesn't reboot02:40
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tcalI'm trying to do a basic build of litex_boards/targets/crosslink_nx_evn.py with the default tools; it builds ok, but doesn't want to load or flash.  The Lattice programmer gives an error; ecpprog says things are fine, but the LED chaser doesn't start.   Could my problem be that I have an ES (eng sample) part?   Or that I'm using Radiant 2.2?   I'm happy to move on to using PrjOxide if that will solve my problems...I was06:28
tcaltrying to do things one step at a time.06:28
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tcalHmm, I'm having better luck using Radiant 2.0.1.  LED chaser is working.   I haven't gotten the Litex> prompt yet, but I suspect my `--serial=serial_pmod0` is getting dropped since the pin assignments for tx/rx aren't correct.07:03
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tcalYeah, `--serial` is ignored.   This is what finally worked for me (using Radiant 2.0.1): `python3 ./crosslink_nx_evn.py --cpu-type=vexriscv --cpu-variant=full --uart-baudrate=115200 --uart-name=serial_pmod0 --build --load`07:35
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gatecattcal: yeah you will need to stick with Radiant 2.0.1 if you have an ES device08:53
gatecat2.1 and later will use the production IDCODE08:53
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leonsI currently have access to a NetFPGA 1G-CML card with a XC7K325T Kintex FGPA (same as used on Genesys2)11:29
leonsI have never ported LiteX to another board (only every used it on my Arty A7)11:29
leonsIs there a rough estimate of how much effort it would be to get it to a basic working state with LiteX? :)11:29
leons(Given that at least the FPGA itself is currently supported in other boards)11:30
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acathla_florent_, I don't understand your patch about up5kspram : https://github.com/enjoy-digital/litex/commit/ad63f8edc852084618ef0c47dfd1e4f9f6e06c19#diff-fda8dafc1cc4c8256b72d8d4f7d8f1199fdb18857680ca958298894c5f75e09812:06
acathlaWhat should I change to so I don't have that warning? I copied the import from the fomu target but still have the warning12:09
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gatecat> Is there a rough estimate of how much effort it would be to get it to a basic working state with LiteX? :)12:53
gatecatime it's usually a couple of days to get a board fully working and debugged12:53
gatecatleons: ^12:53
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leonsgatecat: That sounds good. I'm somewhat optimistic because there's at least schematics and everything, but I don't quite know what to expect :)13:06
acathla_florent_, forget about it, I had an import still importing the wrong file13:18
_florent_acathla: I'm indeed trying to mode all the Retro-compatibility code (mess? :)) to a single location: litex.compat.  up5kspram was already an empty file with just a redirection.14:02
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tcal@gatecat thanks, I'm installing PrjOxide right now, really excited about seeing it work on NX!15:17
gatecatadding `--toolchain oxide --nexus-es-device` to the LiteX command line should be enough to enable it15:17
sajattack[m]anyone have any ideas why the litex kernel driver is hanging or crashing my pc?15:26
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_florent_sajattack[m]: I'm going to rebuild the Acorn PCIe to verify15:57
sajattack[m]thanks _florent_15:57
sajattack[m]btw I'm using pcie 4 I think15:57
sajattack[m]but it should be backwards compat?15:58
sajattack[m]https://www.asus.com/Motherboards-Components/Motherboards/All-series/PRIME-B550M-A-CSM/15:59
tpbTitle: PRIME B550M-A/CSM｜Motherboards｜ASUS Global (at www.asus.com)15:59
sajattack[m]the top m.2 slot15:59
_florent_yes, number of lanes and speed is negiociated at startup15:59
sajattack[m]built from commit ef6620316:02
sajattack[m](litex-boards)16:03
_florent_OK, so just loading the kernel module is crashing your PC?16:06
tcal@gatecat Hmm, just updated & rebuilt yosys/nextpnr-nexus, getting this: `ERROR: Unsupported PDC command 'get_pins'`, `File "/home/tim/enjoy-digital/litex/litex/build/lattice/oxide.py", line 101, in _run_script  raise OSError("Error occured during Yosys/Nextpnr's script execution.")`.    The offending line seems to be `create_clock -period 13.333333333333334 -name PLL_0_P [get_pins PLL_0.PLL_inst/CLKOP]`16:16
gatecatah right, I will work on a fix for that. for now most of my testing has been with the VIP not the EVN16:16
gatecathave created https://github.com/YosysHQ/nextpnr/issues/647 so I don't forget16:19
tcal@gatecat awesome 😀16:20
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gatecattcal: https://github.com/YosysHQ/nextpnr/pull/64816:41
gatecatseems to build with that patch16:41
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MelkhiorFor the more alphabet-inclined among you, following Dolu1990's quick correction of a minor bug affecting C+FD, VexRiscv can now be used as a RV32IMAFDCBK core in LiteX and presumably other SoCs:-)  That's a lot of letter for a a small core (can be abreviated to RV32GCBK but where is the fun in that ?)17:10
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tcal@gatecat -- confirmed it works!   -- on the board, have litex> prompt.  Used `./crosslink_nx_evn.py --cpu-type=vexriscv --cpu-variant=full --uart-name=serial_pmod0 --uart-baudrate=115200  --nexus-es-device  --toolchain=oxide  --build` and ecpprog (nx_support branch).17:38
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_florent_sajattack[m]: here is a bitstream I just tested on the Acorn: https://github.com/litex-hub/litex-boards/files/6206784/sqrl_acorn_cle_215_pcie_2021_03_25.zip17:46
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mithroBTW -- Have people seen alexforencich's work like https://github.com/alexforencich/cocotbext-pcie (and https://github.com/alexforencich?tab=repositories)?17:59
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_florent_mithro: alexforencich's work is very interesting yes, the cocotbext-pcie project could be interesting to replace the simple model I created for LitePCIe:18:13
_florent_https://github.com/enjoy-digital/litepcie/tree/master/test/model18:13
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mikeK_de1socI just noticed that I am getting a update error:  SoCSDRAM is deprecated since 2020-03-24 and will soon no longer work, please update. Switch to SoCCore/add_sdram/soc_core_args instead...........thanks :)18:26
mikeK_de1socIs there a procedure for this?   thanks!18:26
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_florent_mikeK_de1soc: yes you can probably just the following import: from litex.soc.integration.soc_sdram import *18:28
mikeK_de1socAh ok... :)18:28
mikeK_de1socthatnks.18:28
_florent_and then replace soc_sdram_args/soc_sdram_argdict with soc_core_args/soc_core_argdict18:29
_florent_as done here:18:29
_florent_https://github.com/litex-hub/litex-boards/commit/5995769b46f9f37ad916b74cbaad12d11a71f9af18:29
_florent_Note that this is not an error since the design will still build, but the compatibility will be removed at some point so I would recommend to update18:30
mikeK_de1socyup...18:30
mikeK_de1socthat's why I am asking...   Thanks!!!  for the help!!   (You are always so helpful Florent!!  :)   )18:31
mikeK_de1socbut I am having another issue building the arrow video terminal.. But this could be at my end...18:31
mikeK_de1socINFO:SoCCSRHandler:leds CSR allocated at Location 6.18:32
mikeK_de1socTraceback (most recent call last):18:32
mikeK_de1soc  File "./arrow_sockit.py", line 202, in <module>18:32
mikeK_de1soc    main()18:32
mikeK_de1soc  File "./arrow_sockit.py", line 186, in main18:32
mikeK_de1soc    soc = BaseSoC(18:32
mikeK_de1soc  File "./arrow_sockit.py", line 166, in __init__18:32
mikeK_de1soc    self.specials += DDROutput(i1=1, i2=0, o=vga_pads.clk, clk=ClockSignal("vga"))18:32
mikeK_de1socAttributeError: 'Record' object has no attribute 'clk'18:32
mikeK_de1socwill dig into it...18:32
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_florent_mikeK_de1soc: I just fixed compilation from others changes I did today:18:37
_florent_https://github.com/litex-hub/litex-boards/commit/b284fe47c375bff11ea89e57a5a48b81588a93da18:37
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_florent_./terasic_sockit.py --with-video-terminal --build is compiling here18:37
mikeK_de1socSWEET!!!18:37
mikeK_de1socOk i guess I am at the bleeding edge....18:38
mikeK_de1socdoes it matter if you do the --build first or last??18:38
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_florent_no, that's similar18:39
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mikeK_de1socOh WOW huge changes...18:41
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mikeK_de1socSorry Florent: another questions, The last link you gave me, is that for all branches? or just the master branch?18:54
mikeK_de1socgone...18:54
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sajattack[m]<_florent_ "OK, so just loading the kernel m"> loading the kernel module crashed a few times, then I got the /dev/litepcie0 showing up, and litepcie_util info made it hang for 30 sec-ish but not reboot19:10
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leonsRegarding building bitstreams for Kintex-7, that unfortunately doesn't work with the WebPACK edition. Given I'm not using it for commercial use (literally evaluating w.r.t to Vivado's terms and conditions), can I use the Vivado Design Suite 30day evaluation license for that?19:37
leonsSorry for asking - this isn't a Vivado license forum, but I really don't understand their approaches to licensing :)19:39
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keesjanybody played with the quickfeather?20:43
keesjI have the hardware , listend to the AMP hour episode on the subject. know about the next *umo device that is supposed to use the EOS S3 but do not quite  understand how to .. get started / why I need the qorc sdk20:45
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gatecat7:37 PM <leons> Regarding building bitstreams for Kintex-7, that unfortunately doesn't work with the WebPACK edition. Given I'm not using it for commercial use (literally evaluating w.r.t to Vivado's terms and conditions), can I use the Vivado Design Suite 30day evaluation license for that?20:54
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gatecatyeah the evaluation license should be fine to get things going20:54
gatecatdoes mean you have a bit of time pressure though :p20:55
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leonsgatecat: yes, that's pretty unfortunate. I would've hoped that one might be able to get 2 evaluation license periods, but efforts in those direction are probably futile20:57
leonsWell, the 30 days should be sufficient, then I can go search for FPGAs of other vendors with more student-friendly licensing schemes20:57
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somlogatecat: nextpnr-xilinx can't happen soon enough! ;)22:29
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