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| sajattack[m] | lspci is supposed to show "Litex..." if the programming worked right? | 04:13 |
|---|---|---|
| sajattack[m] | Not Squirrel Research Acorn CLE-215+ | 04:14 |
| hansfbaier | sajattack[m]: IIRC it shows something like 'Xilinx Memory Device' | 04:30 |
| hansfbaier | sajattack[m]: let me boot up my test PC.. | 04:31 |
| hansfbaier | sajattack[m]: 02:00.0 Memory controller: Xilinx Corporation Device 7024 | 04:37 |
| hansfbaier | sajattack[m]: in the build dir then there are driver/kernel which contains the kernel module (which you have to insert) and driver/user there is a tool to access the kernel driver | 04:39 |
| sajattack[m] | Ok | 04:40 |
| hansfbaier | sajattack[m]: also, you might want to reboot the PC after flashin | 04:40 |
| hansfbaier | sajattack[m]: you can also use this script instead of rebooting: https://pastebin.com/QduqtS5C | 04:42 |
| tpb | Title: #!/bin/bash# path to the xilinx device on your PC vvvvvvvvvvvvvvcd /sys/devi - Pastebin.com (at pastebin.com) | 04:42 |
| hansfbaier | sajattack[m]: of course all of that has to be run as root | 04:43 |
| hansfbaier | sajattack[m]: What JTAG do you use with the Xilinx? I only had success with FTDI FT2232 | 04:44 |
| sajattack[m] | Yeah I'm having bad luck with jlink | 04:47 |
| hansfbaier | sajattack[m]: This adapter is $7 (with shipping) and works like a charm: https://www.aliexpress.com/item/32817551273.html?spm=a2g0s.9042311.0.0.73c54c4dQG2rnK | 04:56 |
| tpb | Title: NEW FT232H Multifunction High Speed USB to JTAG UART/ FIFO SPI/ I2C Module|uart usb|usb jtagusb uart - AliExpress (at www.aliexpress.com) | 04:56 |
| sajattack[m] | Yeah but shipping will take a month | 04:56 |
| sajattack[m] | I might see if the local electronics shop has ftdi cables | 04:56 |
| hansfbaier | which FPGA loader do you use? openocd? | 04:57 |
| sajattack[m] | Yes | 04:57 |
| hansfbaier | FT2232* also work very well | 04:58 |
| hansfbaier | sajattack[m]: they only have two interfaces instead of one and cost a bit more | 04:58 |
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| nats` | hello, is there a recommended module to instantiate an i2c to drive a mdio interface ? | 08:48 |
| zyp | mdio is not i2c | 08:51 |
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| zyp | there's a mdio module in liteeth, but as far as I can see it just exposes the signals as register for software bitbanging: https://github.com/enjoy-digital/liteeth/blob/master/liteeth/phy/common.py#L30 | 08:54 |
| zyp | yeah, here's the software to drive it: https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/libliteeth/mdio.c | 08:56 |
| nats` | I agree it's not but I always drived it with hardware i2c module | 09:01 |
| nats` | I'll take a look | 09:01 |
| zyp | I find that hard to believe, i2c and mdio is incompatible both at the electrical and the protocol level | 09:03 |
| nats` | oO | 09:09 |
| nats` | uhhmm looking at the code I modified it "a little" :D | 09:14 |
| nats` | I could reuse my verilog code need to find a way to include it in the project | 09:17 |
| zyp | https://m-labs.hk/migen/manual/fhdl.html#instance | 09:19 |
| tpb | Title: The FHDL domain-specific language Migen 0.8.dev0 documentation (at m-labs.hk) | 09:19 |
| frubbl | nats: https://github.com/enjoy-digital/litex/wiki/Reuse-A-Verilog-VHDL-nMigen-Core | 09:34 |
| frubbl | nats: The nmigen example is superset of using verilog code | 09:35 |
| nats` | thanks I'm applying it | 09:44 |
| nats` | maybe a stupid question, but is there a documentation somewhere on how to choose the soc ? | 09:45 |
| frubbl | nats: You mean the base class? Well I just looked at the code, what the features the different base classes have and picked the one that comes closest to what I need. | 09:57 |
| nats` | I mean using other soc like vexrisc or other (I'm a total beginner with this kind of workflow) | 09:59 |
| frubbl | nats: You mean which processor core? | 10:02 |
| frubbl | If you want the smallest possible core (slow!) use serv | 10:04 |
| frubbl | If you want something space efficient which can run linux, use vexriscv | 10:04 |
| frubbl | If you want an embedded core for bare metal, choose picorv32 | 10:05 |
| frubbl | If you want a PowerPC core, use microwatt | 10:05 |
| frubbl | If you want a very space efficient core which can run linux, use mor1kx (OpenRISC architecture) | 10:05 |
| frubbl | If you want a RISC-V core for embedded which is written in nmigen, use minerva | 10:06 |
| frubbl | If you want a super powerful RISCV core which runs linux choose Rocket | 10:07 |
| frubbl | If you are nostalgic and like obsolete FPGA vendor softcores, use lm32 | 10:08 |
| frubbl | nats: But most of the time you'd probably want vexriscv, that's why it is default | 10:10 |
| nats` | ah so SoCCore is a vexrisc ? | 10:13 |
| nats` | I'm browsing the source I'm lost sorry | 10:13 |
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| frubbl | No SocCore is the a base class other SoC s are built on. VexRiscV is the CPU core | 10:21 |
| frubbl | IIRC | 10:21 |
| frubbl | It's quite a learning curve, that's for sure, but Python code is very well written and well worth the read | 10:23 |
| frubbl | s/Python/the Python/ | 10:23 |
| frubbl | I learnt a ton reading _florent_'s code and I still do | 10:25 |
| frubbl | nats` ^ | 10:25 |
| frubbl | It's some of the best code I've ever seen | 10:27 |
| nats` | I'm diving in right now :) | 10:28 |
| nats` | uhhmm I think I found it " cpu_type = "vexriscv"," in soc_core.py | 10:30 |
| nats` | maybe it worth using an integration for an ide because it's a long dive when you use sublime text and grep :D | 10:32 |
| frubbl | nats`, yes the cpu_type is an argument to the SoC | 10:39 |
| frubbl | Great you found it out! | 10:40 |
| frubbl | way to go! | 10:42 |
| nats` | vscode is cool, just loading the code is enough to get the navigation through source | 10:43 |
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| frubbl | nats` Yes it is awesome | 10:57 |
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| _florent_ | nats`: just for info, in the long term, I would like the SoCs to be only based on SoC or LiteXSoC (from soc.py) and completely remove soc_core.py and soc_sdram.py, but for retro-compatibility reasons, soc_code/soc_sdram are still there and mostly wrapping things around soc.py | 13:33 |
| _florent_ | nats`: so the interesting parts are in soc.py | 13:34 |
| _florent_ | Otherwise, VexRiscv is the default CPU (because probably the more polyvalent) but you can change it with --cpu-type on your target or cpu_type parameter on SoCCore | 13:36 |
| acathla | _florent_, shouldn't you write that somewhere, like directly in the files? | 13:37 |
| _florent_ | acathla: That's in SoCSDRAM: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc_sdram.py#L9-L12 | 13:38 |
| _florent_ | that was also in SoCCore, but I remove it since we are still using SoCCore in the targets and was not sure it would be confusing or not | 13:39 |
| acathla | ok | 13:39 |
| _florent_ | I'll add it back when all the targets will be adapted to use LiteXSoC | 13:39 |
| _florent_ | and I'll then hide soc_core/soc_sdram somewhere in the codebase to still allow it to be used but not encourage it :) | 13:40 |
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| nats` | _florent_, I'm making note about everything causing me trouble as a newcomer | 14:51 |
| nats` | maybe it can be helpful to indicate some documentation work or something like that | 14:51 |
| keesj | nats`: I am also using vscode and recently starting using devcontainers (docker stuff) I can now clone my repo and the docker container will build all I need (yosys from source) and then clone litex | 15:01 |
| keesj | (to be fair.. I also have tmux and vim and such installed and .. use the terminal a lot). for the flashing I still have some tools outside of the container but with lxserver I might be able to do additional magic | 15:04 |
| keesj | stuff keeps slowly changing and my personal progress is slow here. | 15:05 |
| keesj | this week-end I hope to just get the default tinyfpga_bx working with the risc core. it currently is not working for me but I don't know why. | 15:07 |
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| keesj | so the address where the bios is storred in the flash of the BX is a bit .. weird it at the end of the program partition while the programming tools so flashing it is not trivial unless I am missing something | 16:55 |
| keesj | this is the layout https://pastebin.com/tzf1q65Y "default" the "user image" if the bitstream , I modified the code to store the bios in the userdata and flashed that that that .. works but I wonder how this was intented to work. perhaps I am missing a step where the bios gets appended to the bitstream | 16:58 |
| tpb | Title: [ { "boardmeta": { "name": "TinyFPGA BX", "fpga": "ice40lp - Pastebin.com (at pastebin.com) | 16:58 |
| keesj | where would something like this happen? | 16:59 |
| keesj | (I am in the bios so.. reached week-end goal) | 17:00 |
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